Method and apparatus for avoiding processor deadly embrace in a

Details Method and apparatus for avoiding processor deadly embrace in a Method and apparatus for avoiding processor deadly embrace in a

1991-10-04

1994-02-01

Evans, Arthur G.

Boots, shoes, and leggings

395800, 3642418, 36424291, 3642524, 36492796, 36492797, G06F 1314

Patent

active

052838706

ABSTRACT:
A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.

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