Method and apparatus for avoiding dicing chip-outs in...

Details Method and apparatus for avoiding dicing chip-outs in... Method and apparatus for avoiding dicing chip-outs in...

2008-04-08

2008-04-08

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

Reexamination Certificate

active

07354790

ABSTRACT:
A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

REFERENCES:
patent: 7087452 (2006-08-01), Joshi et al.
patent: 2002/0098623 (2002-07-01), Akram
patent: 2003/0082836 (2003-05-01), Fetterman et al.
patent: 2003/0162368 (2003-08-01), Connell et al.
patent: 2006/0079024 (2006-04-01), Akram

Affiliated with

Also associated with

Rating

Method and apparatus for avoiding dicing chip-outs in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for avoiding dicing chip-outs in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for avoiding dicing chip-outs in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2774665