Method and apparatus for avoiding deadlock in a computer system

Details Method and apparatus for avoiding deadlock in a computer system Method and apparatus for avoiding deadlock in a computer system

1993-12-21

1994-10-11

Ray, Gopal C.

Boots, shoes, and leggings

364240, 3642402, 3642813, 3642815, 364DIG1, G06F 1314

Patent

active

053554558

ABSTRACT:
A method and an apparatus to avoid a deadlock in a computer system with several busses connected by a bus adapter. If units of different busses of the computer system simultaneously start operations for which more than one bus is needed, it may come to a deadlock. By introducing a BUS SUSPEND signal to one of the busses and adapting the bus-protocol to honor this signal at distinct time slots, deadlock situations are avoided.

REFERENCES:
patent: 3947818 (1976-03-01), Kobayashi
patent: 4403285 (1983-09-01), Kikuchi
patent: 4449183 (1984-05-01), Flahive et al.
patent: 4494193 (1985-01-01), Brahm et al.
patent: 4602327 (1986-07-01), LaViolette et al.
patent: 4737932 (1988-04-01), Baba
patent: 4791554 (1988-12-01), Hirota et al.
patent: 4868741 (1989-09-01), Gula et al.
patent: 4935868 (1990-06-01), DuLac
patent: 5016167 (1991-05-01), Nguyen et al.
patent: 5121487 (1992-06-01), Bechtolsheim
patent: 5133074 (1992-07-01), Chou
patent: 5150467 (1992-09-01), Hayes et al.
"The 8th Annual Symposium on Computer Architecture" IEEE & Assoc. for Comp. Mach., pp. 107-133, May 12-14, '81.

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