Boots – shoes – and leggings
Patent
1996-03-21
1997-12-30
Ngo, Chuong D.
Boots, shoes, and leggings
364488, G06F 752, G06F 1500
Patent
active
057038023
ABSTRACT:
In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.
REFERENCES:
patent: 4896272 (1990-01-01), Kurosawa
patent: 5060183 (1991-10-01), Sakashita et al.
patent: 5333032 (1994-07-01), Matsumoto et al.
patent: 5345393 (1994-09-01), Ueda
patent: 5351206 (1994-09-01), Yang et al.
Nishiyama Tamotsu
Tsubata Shintaro
Matsushita Electric - Industrial Co., Ltd.
Ngo Chuong D.
LandOfFree
Method and apparatus for automatically designing logic circuit, does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for automatically designing logic circuit, , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for automatically designing logic circuit, will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-208952