Boots – shoes – and leggings
Patent
1996-08-02
1999-03-30
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, 395500, G06F 1750
Patent
active
058896856
ABSTRACT:
Short-circuit current and power consumption for an integrated circuit may be calculated by measuring short-circuit current for various cells within an integrated circuit using a Verilog.TM. logic level model of the cell. Each cell within an integrated circuit may be characterized by its inputs and outputs and connectivity. A corresponding SPICE sub-circuit model having the same logic characteristics as the cell may be generated. A number of calculation passes are made for each sub-circuit within a cell to determine short circuit current for each sub-circuit at various signal rise and fall times and for various inputs and outputs. Current data may be stored in a format compatible with Verilog.TM. propagation delay data. Overall power consumption and short circuit current for an integrated circuit may then be calculated from Verilog.TM. logic model data. The use of the Verilog.TM. model eliminates the need to calculate short circuit current at a SPICE circuit level. Moreover, putting short circuit data into a propagation delay format allows software to more readily process short circuit data.
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Verilog LRM Reference Manual Chapters 1, 6, 7 and 12, Version 1.0.
Bell Robert P.
Cirrus Logic Inc.
Fink Mark J.
Shaw Steven A.
Teska Kevin J.
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