Patent
1995-11-17
1997-09-02
Oberley, Alvin E.
395709, 395588, G06F 945
Patent
active
056641931
ABSTRACT:
Apparatus and methods are disclosed for determining a load latency value to use in scheduling instructions for a target program, (the load latency value is the separation between a load command and the using instruction, wherein the expected return of the data is a function of where in the system the requested data resides). The instruction scheduling function is the modulo scheduling function of an optimizing compiler. Most modem microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units and typically multi-level memory devices such as on-chip cache, off-chip cache as well as main memory. For such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduling loops in the target program code. The invention consists of a technique to determine an optimal load latency value given an rmii vector, which is a set of rmii values which correspond to different values of instruction load latency. The disclosed invention makes the determination of the optimal load latency an automatic feature of the optimizing compiler thereby not requiring the user to specify the load latency and or change the specified load latency values if the target program is to be recompiled to run on a different target computer platform.
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Basinski Erwin J.
Chaki Kakali
Oberley Alvin E.
Sun Microsystems Inc.
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