Patent
1989-01-24
1992-07-07
Fears, Terrell W.
395425, G06F 1200, G06F 1300
Patent
active
051290693
ABSTRACT:
A memory system includes a memory unit with plural addressable storage locations, a connector arrangement for detachably electrically coupling the memory unit to a computer, and a decoding arrangement for determining whether a computer memory address is within a range of addresses to which the memory unit is to respond, the decoding arrangement including a base address register storing a value representing the first address in the range and a size register defining the number of addresses in the range. A method by which a computer can automatically configure this system includes the steps of determining a base address to be associated with the connector, loading into the base address register a value representing the base address, loading into the size register a value representing the maximum range of addresses, thereafter selectively accessing storage locations to determine the actual number of contiguous locations in the memory unit, and then changing the size register, when the actual number of locations is less than the maximum range of addresses, to a value representing the actual number of locations.
REFERENCES:
patent: Re31318 (1983-07-01), Kaufman et al.
patent: 3781812 (1973-12-01), Wymore et al.
patent: 3815103 (1974-06-01), Holtey et al.
Helm Gordon L.
McAuliffe William J.
Nicol Mark D.
Olson Anthony M.
Witkowski Todd R.
Fears Terrell W.
Whitfield Michael A.
Zenith Data Systems Corporation
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