Method and apparatus for automatic functional speed setting of a

Pulse or digital communications – Spread spectrum – Direct sequence

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370 84, H04L 2300, H04J 322

Patent

active

052475468

ABSTRACT:
A system implemented in a Data Circuit Terminating Equipment (DCE), interfacing between a user's data processing equipment and a digital network, comprises a detector for generating an Analog Carrier Detect (ACD) DCE internal signal as well as an Analog Squared Data (ASD) DCE internal signal, and an ASD WIDTH ERROR DCE internal signal from the flow of data transmitted by the network and received on the DCE receive line. The system also comprises new circuitry for generating a Lack of Receiver Timing (LRT) DCE internal signal, a Block Error ASD DCE internal signal, and a Block Error Bipolar (BEBIP) DCE internal signal. Finally, the system includes a logical decision process which leads the DCE to automatically adjust its functional speed to the rate of data transmitted by the network and received on DCE receive line. The process includes setting the DCE to the highest possible functional speed, and for that particular speed, checking all four of the ACD, LRT, BEASD and BEBIP DCE internal signals; and if one of the checkings is not satisfactory, setting the DCE to the next possible lower speed, or if all checkings are satisfactory, stopping the process as the DCE is ready to work.

REFERENCES:
patent: 3747074 (1973-07-01), Schulze
patent: 4168401 (1979-09-01), Molleron et al.
patent: 4229815 (1980-10-01), Cummiskey
patent: 4485468 (1984-11-01), Slana
patent: 4756007 (1988-07-01), Qureshi et al.
patent: 4887083 (1989-12-01), Kosugi et al.
Patent Abstracts of Japan, vol. 8, No. 21 (E-224)(1458) Jan. 29, 1984, & JP-A-58 182330 (Ricoh K.K.) Oct. 25, 1983.
Patent Abstracts of Japan, vol. 10, No. 283 (E440(2339) Sep. 26, 1986 & JP-A-61 101138 (Hitachi Ltd) Apr. 20, 1986.

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