Data processing: measuring – calibrating – or testing – Calibration or correction system – Signal frequency or phase correction
Reexamination Certificate
2007-09-18
2007-09-18
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Signal frequency or phase correction
C327S161000, C327S293000, C702S079000
Reexamination Certificate
active
11400447
ABSTRACT:
An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.
REFERENCES:
patent: 5438259 (1995-08-01), Orihashi et al.
patent: 5488369 (1996-01-01), Miller
patent: 6211714 (2001-04-01), Jeong
patent: 6242959 (2001-06-01), Stern
patent: 6373307 (2002-04-01), Takai
patent: 6396322 (2002-05-01), Kim et al.
Analog Devices Inc.
Barlow John
Koppel, Patrick, Heybl & Dawson
Le John
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