Method and apparatus for at speed observability of pipelined cir

Details Method and apparatus for at speed observability of pipelined cir Method and apparatus for at speed observability of pipelined cir

1996-06-12

1998-04-14

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057401810

ABSTRACT:
The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

REFERENCES:
patent: 5530706 (1996-06-01), Josephson et al.
patent: 5535331 (1996-07-01), Swoboda et al.
1996 IEEE Int. Solid-State Circuits Conference, pp. 354-355.
IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1-1990).

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