Static information storage and retrieval – Addressing – Multiplexing
Reexamination Certificate
2000-09-05
2002-04-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Multiplexing
C365S233100, C365S230080
Reexamination Certificate
active
06366523
ABSTRACT:
TECHNICAL FIELD
This invention relates to synchronous memory devices, and more particularly, to a method and apparatus for more quickly processing addresses applied to synchronous memory devices.
BACKGROUND OF THE INVENTION
Memory devices are in widespread use in computers, particularly personal computers. The system memory of such computers is generally provided by dynamic random access memories (“DRAMs”). DRAMs were initially asynchronous in which commands and addresses were received and processed by DRAMs at a rate that was not determined by a periodic signal. However, in an attempt to reduce memory access times and facilitate pipelining of memory accesses. synchronous DRAMs (“SDRAMs”) were developed.
In a SDRAM, memory accesses are synchronized to an external clock that is applied to the DRAM so that one memory access, i.e., a read or write, occurs each period of the clock. An example of a conventional SDRAM
40
is shown in FIG.
1
. The SDRAM
40
has as its central memory element a memory array
42
that is segmented into two banks
44
,
46
. The SDRAM
40
operates under control of a control logic
48
that receives a system clock signal CLK, a clock-enable signal CKE, and several command signals that control reading from and writing to the SDRAM
40
. Among the command signals are a chip-select signal CS*, a write-enable signal WE*, a column address strobe signal CAS*, and a row address strobe signal RAS*. (The asterisk next to the command signals CS, WE, CAS, and RAS indicate that these signals are active low signals, i.e., the command signals CS*, WE*, CAS*, and RAS* go to a low logic level when active).
In addition to the command signals, the SDRAM
40
also receives addresses from an address bus
52
, and receives or outputs data on a data bus
60
. The received addresses are either bank/row addresses or column addresses. An address on the address bus
52
is designated as a row addresses by a row address strobe RAS* signal transitioning active low when the address is present on the address bus. An address on the address bus
52
is designated as a column addresses by a column address strobe CAS* signal transitioning active low when the address is present on the address bus. As explained below, column addresses can also be generated internally. In any case, addresses from the address bus
52
are clocked into the SDRAM
40
through an address register or address latch
62
. If an address is a row address, the address is coupled to the array
42
through a row address path
64
. The row address path
64
includes a row address multiplexer
66
that receives the external row address from the address latch
62
and receives an internal row address from a refresh circuit
67
. The row address multiplexer
66
provides the row addresses to either of two row address latches
70
depending upon the logic state of the bank address BA. The row address latches
70
latch the row addresses and provide the row addresses to respective row decoders
72
. The row decoders
72
take the 11-bit address from the row address latch
70
and activate a selected one of 2,048 row address lines
73
. The row address lines
73
are conventional lines for selecting row addresses of locations in the memory array
42
. As noted above, the following discussion assumes that the row address has been selected and that the selected row is activated.
After a row address has been received and latched by RAS* going low, a column address may be latched responsive to a column address strobe signal CAS* going active low. If the address received at the address latch
62
is a column address, it is transmitted to the I/O interface
54
and the memory array
42
through a column address path
76
. The column address path includes a column address counter/latch
78
that receives an initial column address from the address latch or buffer
62
and thereafter increments the address once each cycle of the CLK signal. The column address from the column address counter/latch
78
is thus an internally generated column address, as mentioned above.
The internal column address from the column address counter/latch
78
and an external column address from the address latch or buffer
62
are each applied to a multiplexer
79
. The multiplexer
79
selects one of these column addresses based on the nature of the current memory access. If the current memory access is one of several identical memory accesses (i.e., a READ or a WRITE) to successive columns of a row, known as a “burst” memory access, the multiplexer
79
selects the internal address from the column address counter/latch
78
unless a new command is received. If, during a burst memory access, e.g., a burst READ, a new command, e.g., a burst WRITE, is received, the multiplexer
79
selects an external column address from the address latch or buffer
62
.
In operation, the SDRAM
40
assumes a number of states before and during a memory transfer. Initially, the SDRAM
40
is in an idle state prior to the start of a memory transfer. When data are to be read from or written to the memory device, a row address is applied to the address bus
52
and an active low RAS* signal is applied to the command decoder in the control logic
48
. Thus, in the idle state, the only address used by the SDRAM
40
is an external row address. There is therefore never any need to use an internal address in the idle state. The transition of the RAS* signal to an active low state transitions the SDRAM
40
from the idle state to the row active state.
During the row active state, the memory cells in a selected row of the array
42
that corresponds to the row address are coupled to respective digit lines. As is well understood in the art, there are a set of complementary digit lines for each column of the memory arrays
42
. Once the SDRAM
40
has transitioned to the row active state, the SDRAM
40
can transition to the column command state responsive to the RAS* signal transitioning high and the CAS* signal transitioning active low. In the column command state, the SDRAM
40
can receive and process a column address and a column command, such as a READ or a WRITE command. Thus, once the SDRAM
40
transitions from the row active state to the column command state, the SDRAM
40
can process a column address that, as explained above, can be either an external column address applied to the address bus
52
or an internal column address generated by the column address counter latch. When a memory command is received that is not for a burst memory access, the multiplexer
79
selects an external column address from the address latch or buffer
62
. In a burst memory transfer, the column address counter/latch
78
increments the initial column address once each cycle of the CLK signal to generate a number of sequential column addresses corresponding to the length of the burst.
After data are read from or written to the SDRAM
40
, the RAS* signal transitions inactive high to transition the SDRAM
40
back to the idle state during which precharging of the array
42
occurs before the start of another memory access.
As explained further below, the time required to determine whether an internal column address or an external column address should be selected by the multiplexer
79
can significantly slow the rate at which memory accesses can occur. The inventive method and apparatus is adapted to allow this determination to be made at an earlier time so that memory accesses can occur at a faster rate.
After the multiplexer has selected either an internal address or an external address, the multiplexer
79
couples the selected column address to a pre-decoder
102
and a latch
82
. The pre-decoder
102
partially decodes the column address and passes it to a column decoder
84
to complete the decoding. The decoder
84
then selects the column to which data are to be read from or written to.
The input data path
56
transmits data from the data bus
60
to the I/O interface
54
. The output data path
58
transmits data from the I/O interface
54
to the data bus
60
.
During a memory
Elms Richard
Nguyen Van Thu
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