Method and apparatus for analyzing the power network of a VLSI c

Details Method and apparatus for analyzing the power network of a VLSI c Method and apparatus for analyzing the power network of a VLSI c

1994-09-22

1997-01-28

Trans, Vincent N.

Boots, shoes, and leggings

364490, G06F 1750

Patent

active

055983480

ABSTRACT:
A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a semiconductor circuit layout. A compacted power network is then derived from the power network. The compacted power network includes a compacted primary resistive network to characterize the electrical resistance of the power trunks within the semiconductor circuit layout. The compacted power network also includes a compacted secondary resistive network to characterize the electrical resistance of power straps that deliver power to transistors within the semiconductor circuit layout. The compacted power network constitutes a network of compaction component values that correspond to functional regions in the semiconductor circuit layout. Each of the compaction component values includes an associated set of spacial compaction values that characterize the total resistance of a functional region. The operation of the compacted power network is simulated on a circuit simulation program to identify areas in the compacted power network that do not comply with predetermined power network performance criteria, such as electromigration limits and voltage drop limits. The semiconductor circuit layout is then reconfigured to satisfy the predetermined power network performance criteria.

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"Optimization of Digital MOS VLSI Circuits" by M. D. Matson, Chapel Hill Conference, 1985, pp. 109-115.
"Automatic Sizing of Power/Ground (P/G) Networks in VLSI" by R. Dutta et al, 26th ACM/IEEE Design Automation Conference, 1989, pp. 783-786.

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