Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-07-26
2011-07-26
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S106000, C703S014000
Reexamination Certificate
active
07987439
ABSTRACT:
Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.
REFERENCES:
patent: 5379231 (1995-01-01), Pillage et al.
patent: 5469366 (1995-11-01), Yang et al.
patent: 6374205 (2002-04-01), Kuribayashi et al.
patent: 7243313 (2007-07-01), Qin et al.
patent: 7283943 (2007-10-01), Qi et al.
patent: 7441213 (2008-10-01), Lehner et al.
patent: 7788079 (2010-08-01), Wu et al.
patent: 2003/0106030 (2003-06-01), Keller et al.
patent: 2004/068507 (2004-12-01), None
Patent Abstracts of Japan, Publication No. 2003-223478, Publication Date Aug. 8, 2003.
Che Hong Bo
Kim Young Hwan
Garbowski Leigh Marie
Perman & Green LLP
Postech Academy-Industry Foundation
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