Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-10-21
2001-08-21
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S260000, C330S292000
Reexamination Certificate
active
06278321
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electrical circuits. In one embodiment, the invention relates to a method or apparatus for providing a variable gain amplifier. In a further embodiment, the invention relates to using a novel complementary metal oxide semiconductor (CMOS) voltage regulator to provide a stable voltage source for a variable gain amplifier.
BACKGROUND OF THE INVENTION
Variable gain amplifier (VGA) circuits are useful in many applications. One particular application is in rechannel cores for disk drives. As is known in the art, such rechannel cores may be embodied as integrated circuits for use in a disk drive. As is known in the art, from the reading head of the disk drive at the edge of the reader arm, an analog-to-analog fixed gain amplifier resides at the disk drive read/write arm. After the read amplifier, a second amplifier is configured to give a constant output signal level. In order for this second amplifier to provide a constant output, it must have a variable gain because the magnitude of the input will vary according to varying operating parameters, such as the head of the disk drive flying closer or further from the magnetic surface, variations in preamplifier gain, or other varying operating parameters.
D. R. Welland et al., “A Digital Read/Write Channel with EEPR4 Detection,”
ISSCC Dig. Tech. Papers,
February 1994, pp. 276-277, discusses one rechannel circuit design. The Welland paper,
FIG. 2
in particular, shows a structure with NMOS inputs, current source loads, source followers, dual single ended feedback, and NMOS GDS sets input transconductance. However, the circuit shown has a current output, an NMOS feedback, and a static control voltage (VCON). This circuit is therefore not suitable for some applications, particularly because common mode input signals modulate the conductance of the gain setting transistor. The present invention instead ties gain control to the VGS of the input NMOS the current sources relative to the CMOS feedback supply voltage regulator, giving superior performance.
G. Vishakhadatta et al., “An EPR4 Read/Write Channel with Digital Timing Recovery,”
IEEE J Solid-State Circuits,
Vol. 33, No. 11 November 1998 pp. 1851-1857 discusses (see
FIG. 4
, p. 1154) a circuit with an input stage that has some similarities to the present invention, but with voltage outputs from the source follower gates, and replacing the NMOS gain control of Welland with a resistor for better linearity. However, the resistor has a fixed conductance, requiring the gain to be set in the feedback devices. In that VGA, I
1
& I
2
, the tail current is used to set the gain, but in an inverse relationship to the present invention, because the current through the input devices sets the feedback conductance, rather than the input conductance.
F. Krummenacher, “A 4 MHz Continuous-time filter with on-chip automatic tuning,” IEEE Journal of Solid-State Circuits, vol. SC-23, pp. 750-758, June 1988, discusses using two NMOS in triode with gates to inputs to linearize transconductance.
What is needed is a method or apparatus that can provide variable gain amplification with high bandwidth, efficiency, and controllable gain and bandwidth.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a method and apparatus for a differential amplifier designed to have a well-regulated common mode output. The invention has particular applications to CMOS integrated circuits used in data reading devices, where it has traditionally been difficult to achieve a low impedance/high frequency voltage source.
In another aspect, the invention provides a method or device for using a variable gain amplifier with a regulated voltage source that has good stability over a wide bandwidth of load changes. The invention has particular applications to CMOS integrated circuits, where it has traditionally been difficult to achieve a low impedance/high frequency voltage source.
The present invention may also be embodied as a digital data storage device, such as a disk drive. Digital data storage devices that record data on a media are ubiquitous in computing, and audio and video signal recording. Such devices include a controller, a read/write head, a mechanism for moving the media in relation to the head, and a media, such as a tape or disk, that can record signals encoding the digital data. A data storage device according to the present invention, provides improved performance due to its improved reading of the physical media.
The present invention may also be embodied as an integrated circuit (IC). Integrated circuits are well known in the art as devices that can perform a wide variety of digital, analog, or digital/analog functions. An IC according to the present invention has improved electrical signal handling capabilities as described above.
In a more specific embodiment, the present invention is a rechannel IC or rechannel IC core for use in a data storage device. A rechannel receives digital bytes from a computing device and encodes those bytes into signals that may be recorded onto a physical media such as a disk drive platter. A rechannel IC or rechannel core built according to the present invention, has improved reading performance because of the good linearity and high bandwidth of the circuit described above.
A further understanding of the invention can be had from the detailed discussion of specific embodiments below.
REFERENCES:
patent: 5384501 (1995-01-01), Koyama et al.
patent: 5386328 (1995-01-01), Chiou et al.
patent: 5852526 (1998-12-01), Huntington
patent: 5894234 (1999-04-01), Morris
“Alpha Introduces The Only Adjustable Shunt Regulator With Superior Performance In Small Outline Surface Mount SOT-23,”Alpha Seminconductor Press Release, Oct. 29, 1998.
Welland et al., “A Digital Read/Write Channel with EEPR4 Detection,”ISSCC Dig. Tech. Papers, Feb. 1994, pp. 276-277.
Gopinathan et al., “A 2.5V, 30MHz-100MHz, 7th-Order, Equiripple Group-Delay Continuous-Time Filter and Variable-Gain Amplifier Implemented in 0.25&mgr;m CMOS,”1999 International Solid-State Circuits Conference, 1999, WA 23.2.
Vishakhadatta et al., “An EPR4 Read/Write Channel with Digital Timing Recovery,”IEEE J. Solid-State Circuits, vol. 33, No. 11 Nov. 1998, pp. 1851-1857.
F. Krummenacher, “A 4MHz Continuous-time filter with on-chip automatic tuning,”IEEE Journal of Solid-State Circuits, vol. SC-23, pp. 750-758, Jun. 1988.
Fish & Richardson P.C.
Infineon Technologies Corporation
Mottola Steven J.
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