Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-09-17
2002-12-31
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S033000, C712S210000, C711S171000, C711S212000, C711S203000, C703S026000, C703S027000
Reexamination Certificate
active
06502181
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the field of methods and devices for digital processors and processor cores. More specifically, the present invention is directed to an enhanced processor that maintains backwards compatibility with a number of.earlier designs in the same family, including earlier processors with different address space and data widths.
BACKGROUND OF THE INVENTION
A large literature exists regarding the history of processor development and evolution. A brief summary of this history is presented below. The reader is referred to infopad.eecs.berkeley.edu/CIC /archive/cpu_history.html and its cited documents for more information.
While processors have evolved dramatically over the last several decades, in many design applications and environments there remains an extensive interest in utilizing mature processor designs. Older designs have the advantage of a well-designed tool set, a large base of engineering expertise and familiarity, and in some cases a large investment in software code.
The Z-80 processor is one older processor design in which there remains a large interest. The Z-80 was originally developed to be a successor to the Intel 8080 and was regarded at the time as a vast improvement. Like the 8080, the Z-80 used 8 bit data and 16 bit addressing. The Z-80 could execute all of the 8080 instructions and included 80 additional instructions (1, 4, 8 and 16 bit operations and block move and block I/O). The register set was doubled from the 8080, with two banks of data registers (including A and F) that could be switched between. This allowed fast operating system or interrupt context switches. The Z-80 also added two index registers (IX and IY) and 2 types of relocatable vectored interrupts (direct or via the 8-bit I register). Aspects of the Z80 are described in U.S. patent application No. 4,332,008.
One characteristic that made the Z-80 popular in designs was the memory interface—the CPU generated its own RAM refresh signals, which meant easier design and lower system cost, the deciding factor in its selection for the Radio Shack TRS-80 Model 1, introduced on Aug. 3, 1977.
Like many processors, the Z-80 featured many undocumented instructions. In some cases, they were a by-product of early designs (which did not trap invalid op codes, but tried to interpret them as best they could), and in other cases chip area near the edge was used for added instructions, but fabrication made the failure rate high. Instructions that often failed were not documented, increasing chip yield. Later fabrication made these more reliable.
After its introduced, many variants of the Z-80 were developed and produced by a variety of manufacturers. A number of these processors were sold with peripheral components included on-chip. More recently, Z80 family processors are developed and distributed as soft-core specifications in a register transfer language (RTL), which can then be combined with other components to produce ASICs.
Hitachi produced the 64180 (1984) with added components (two 16 bit timers, two DMA controllers, three serial ports, and a segmented MMU mapping a 20 bit (1M) address space to any three variable sized segments in the 16 bit (64K) Z-80 memory map).
Zilog produced the Z-180, compatible with Z-80 peripheral chips, plus variants (Z-181, Z-182). The Z-280 was a 16 bit version introduced about July, 1987, with a paged (like Z-180) 24 bit (16M) MMU (8 or 16 bit bus resizing), user/supervisor modes and features for multitasking, a 256 byte (4-way) cache, 4 channel DMA, and a large number of new op codes added (total of almost 3,500, including previously undocumented Z-80 instructions).
A 16/32 bit Z-380 version also exists (1994) with an added 32-bit linear addressing mode that is not Z-80 compatible.
Z380
Another addition to the Z80 family is the Z380. While the Z380 was intended as an advanced 32-bit version of the Z80, with 16 Mb linear addressing, the processor had mixed results. One problem was that Z80 binary code could not run on the 380 without recompiling, therefore Z380 systems were not “turn-key” compatible with software written for the Z80. A further difficulty is that the Z380 mechanisms for extending the capabilities of the Z80 and Z180, while maintaining binary program compatibility, were inconvenient for both assembly-language programmers and C compiler writers, and expanded the code space requirements for both kinds of programs. The Z380's multi-byte op-code prefixes meant that every time a 24- or 32-bit address or data value was used in an instruction, the instruction not only had to extend by the necessary 8 or 16 bits, but by another 16 bits of “DDIR prefix” as well. This has proved to be linear addressing and wider data at too high a price in code size.
Despite all the further developments made in mP design since 1977, there remains continuing interest in Z80-based processing. For many computer control applications, Z80 processing remains a versatile, reliable and inexpensive solution. As a result of this continued interest, a substantial body of tools and support components for the Z80, including emulators, compilers, etc. continues to be distributed. See, for example, the resources listed at www.geocities.com/SiliconValley/Peaks/3938/z80_home.htm.
Zilog, Inc., continues to produce a sell a number processors in the Z80 family. A brief comparison of the features of these processors is presented in the table below. Further information is available at http://www.zilog.com/resources/ z80r.html.
Z80/Z180/Z380 Comparison
Z80
Z180
Z380
External Data Bus Width
8-bit
8-bit
16/32-bit
Address Space
64k
1 Mb
16 Mb Linear
Number of register sets
2
2
8 16-bit
Number of register planes
1
1
4
Static core
no
yes
yes
CPU Speed
10
33
33
Clocks/Inst. Min
4
3
2
Memory Management
An important enhancement in processor design is the ability to address a large address space. The address space is determined by the number of bits the processor can manipulate and output as an address
Most 8 bit processors are limited to addressing 64k of memory, using two 8-bit words to address each memory location. A 16 bit CPU generally can support 1 to 16 Mb of memory. To support these larger address spaces, the processes generally utilize a memory management unit (MMU) to access an address space larger than 64k, but still maintain compatibility with earlier instruction sets. Under one MMU scheme, all instructions, in all modes, issue 16 bit addresses. The MMU converts these 16 bit addresses to 20 bits.
In such a scheme, physical memory generally refers to the entire universe of memory addressible by the processor. The memory that can be addressed with any one map, or configuration, of the MMU is called the logical address space. In this scheme, every address generated by a user's program is a logical address and the MMU's role is to translate these logical addresses into physical ones. On power up, the MMU may translate every logical address to exactiy the same physical address (which simulates the Z80).
In an MMU scheme, address references made by a program is passed through the MMU before being presented to the physical memory space. If the address matches a range previously programmed into the MMU, then the MMU will add an offset to that address, forming the physical address.
Exd Z80
A number of years ago, Zilog purchased the exclusive rights to the Exd Z80 softcore. One advantage of the ExdZ80 was its single clock bus cycles. As implemented and marketed, the core was “pure” Z80, even including hidden Z80 instructions from 1975.
While the Z180 family has long advertised 20-bit address capability, its mechanism for achieving this, called the Memory Management Unit or MMU, is difficult to use and has impeded the use of this family into larger-scale applications. One would like to add a 24-bit mode in which the processor automatically fetches longer addresses and data, so that no prefix is required for most instructions.
What is needed is a processor “between” the Z18x and Z38x families, that provides 24-bit linear addressing, is more natural and conv
MacKenna Craig
Yearsley Gyle
Pan Daniel H.
Skjerven Morrill LLP
ZiLOG, Inc.
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