Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-29
2003-02-04
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185280, C365S185290, C365S189110, C327S536000, C327S589000
Reexamination Certificate
active
06515901
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of non-volatile read-only memories. More specifically, the present invention relates to an apparatus, method, and system for allowing continuous application of high voltage to a non-volatile memory device power pin.
BACKGROUND OF THE INVENTION
Metal-oxide-semiconductor (“MOS”) flash memory devices typically use memory cells having electrically isolated gates, called floating gates. The floating gates are typically surrounded by a dielectric insulator and formed from a polycrystalline silicon (polysilicon) layer. The electrical insulation is typically provided by a silicon dioxide layer. Information is stored in the memory cell as electrical charge on the floating gates. Charge is transferred through the silicon dioxide layer to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc., depending on the construction of the memory cells.
A cross-sectional view of a typical floating gate flash EEPROM cell
100
is shown in FIG.
1
. In
FIG. 1
, the flash memory cell
100
is formed on a silicon substrate such as the p-type substrate
115
. The flash cell
100
includes a pair of spaced-apart doped regions
112
and
113
disposed in substrate
115
. Region
113
comprises a source and region
112
comprises a drain. The source
113
and the drain
112
define an active silicon region
104
and a channel between the source
113
and the drain
112
. A polysilicon floating gate
110
is disposed above and between the drain
112
and source
113
and insulated therefrom by a thin layer of silicon dioxide or other electrically insulative layer
114
. Insulative layer
114
is generally known as the gate or tunnel oxide, having a typical thickness of approximately 110 angstroms (.ANG.). The floating gate
110
is insulated from a second control gate
111
disposed above floating gate
110
and insulated therefrom by an interpoly dielectric layer
109
. Interpoly dielectric layer
109
may be variously formed of a single layer of silicon dioxide, or of an oxide/silicon nitride/oxide multilayer dielectric of appropriate thickness. The control gate
111
is fabricated from a second layer of polysilicon deposited subsequent to the interpoly dielectric layer
109
.
Since memory cells and peripheral transistors in a flash memory device have thin tunnel oxide layer, if a high voltage such as 12 volts is continuously applied to these cells and peripheral transistors, degradation or breakdown of the tunnel oxide layer may occur after some time due to the high electric field impressed across the thin oxide. This is especially true with respect to the programming voltage source switches which connect the flash cell transistors to the programming high voltage power supplies (e.g., VPP). Unlike the flash cell transistors in the memory array or peripheral transistors in the program or erase circuitry which only briefly see programming or erase voltages when the respective cells are either programmed or erased, the source switches are constantly, for their lifetimes, exposed to the high programming voltages. To increase circuit speed and packing densities, devices are being scaled more and more. Scaling refers to procedures wherein circuit dimensions and device structures are shrunk in proportion to one another to produce a smaller device which still functions according to parameters known to be functional on larger unscaled devices. One consequence of device scaling is that when all transistor dimensions are reduced, the insulative gate oxide between the substrate channel and the control gate is reduced proportionally. The thinner oxide produced for the scaled array and peripheral devices are problematic for those peripheral devices (e.g., voltage switches) that are exposed to voltages that are higher than voltages applied to the array cells and for longer periods of time. A leading example of devices which suffer as a result of scaling are the transistors that function as source switches connecting flash memory cells to the programming voltage power supplies (e.g., VPP). Whereas the flash memory cells and other peripheral transistors may only be connected to the programming high voltage for a short period of time to program or erase the cells, the source switches are continuously exposed to the high voltage power supply used for programming and erasing the flash memory cells. Because of the limitations just described, current specification for a typical flash memory device includes a constraint that VPP that is greater than a certain voltage level (e.g., 8 volts) can be applied for only a maximum period of time (e.g., 80 hours) over the lifetime of the flash memory device. Consequently, to operate within this constraint, the flash memory device should only be connected to the high voltage VPP for programming or erase operations and should be disconnected from the high voltage VPP source when those operations are done. Such a configuration negatively affects the performance of the flash memory because the VPP source has to be connected to and disconnected from the flash memory device numerous times depending upon whether memory operations requiring the high voltage VPP are being performed. Accordingly, there exists a need for continuous application of high voltage to a flash memory device power pin (e.g., VPP) without damaging the peripheral transistors, especially the switching transistors.
REFERENCES:
patent: 5095461 (1992-03-01), Miyakawa et al.
patent: 5617359 (1997-04-01), Ninomiya
patent: 5625211 (1997-04-01), Kowshik
patent: 5691944 (1997-11-01), Kondoh
patent: 5812018 (1998-09-01), Sudo et al.
patent: 6038190 (2000-03-01), Kowalski et al.
patent: 6288941 (2001-09-01), Seki et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Ho Hoai
Intel Corporation
LandOfFree
Method and apparatus for allowing continuous application of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for allowing continuous application of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for allowing continuous application of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3152309