Method and apparatus for aligning an integrated circuit chip

Details Method and apparatus for aligning an integrated circuit chip Method and apparatus for aligning an integrated circuit chip

2000-04-05

2001-03-06

Abrams, Neil (Department: 2839)

Fishing, trapping, and vermin destroying

C439S571000

Reexamination Certificate

active

06196849

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable
BACKGROUND OF THE INVENTION
The present invention is generally related to mounting an integrated circuit chip on a printed circuit board, and more particularly to a socket that facilitates mounting and alignment of an integrated circuit chip on a printed circuit board.
Sockets for mounting electronic devices such as integrated circuit chips on a printed circuit board are known. The socket may be mounted to the printed circuit board, while the integrated circuit chip is snap-fitted into the socket. One advantage of this arrangement is that, unlike integrated circuit chips that are soldered directly on the printed circuit board, an integrated circuit chip that is mounted in a socket can be easily disconnected from the printed circuit board for testing and replacement. However, the relatively dense layout and small size of electrical contacts on some integrated circuit chips necessitates precise alignment both between the socket and the printed circuit board, and between the integrated circuit chip and the socket.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, an integrated circuit alignment feature facilitates alignment of an integrated circuit chip relative to a socket, and a socket alignment feature facilitates alignment of the socket relative to a printed circuit board. The socket includes four walls that define a rectangular frame in which the integrated circuit chip is mounted. A first alignment contact point extends inward relative to a first one of the walls. Second and third alignment contact points extend inward from a second one of the walls, which adjoins the first wall. A first force is applied against the integrated circuit chip from a third one of the walls, which is parallel with the first wall. Second and third forces are applied against the integrated circuit chip from a fourth one of the walls, which is parallel with the second wall. Hence, the integrated circuit chip is aligned in a corner defined by the first and second walls, and is oriented by the three alignment contact points. Spring members may be employed to provide the first, second and third forces.
The socket alignment feature includes first and second alignment posts that are disposed proximate to opposing corners of the socket. The first alignment post provides a point around which the socket can be rotated when the first alignment post is fitted into a receiver hole in the printed circuit board. The second alignment post secures the socket in position at one point in the circle of rotation defined by the first alignment post. In the illustrated embodiment, the first alignment post has a triangular shaped cross-section and the second alignment post has a diamond-shaped quadrilateral cross-section.
The socket may be secured to the printed circuit board with captive hardware fasteners that facilitate application of constant, known force to secure the socket against the printed circuit board. Each fastener includes a head and a shaft on which a spring member is retained. The spring is retained by forming a channel in the shaft of the fastener where the shaft and head portions meet. At least one turn of the spring member is retained in the channel, thereby securing the spring to the fastener. A retaining washer may be disposed at one end of the spring such that the spring is disposed between the head of the fastener and the retaining washer. The retaining washer functions to hold the spring in compression relative to the free length of the spring. Use of the retaining washer enables application of higher spring force with a shorter shaft length.


REFERENCES:
patent: 4734043 (1988-03-01), Emert et al.
patent: 5161983 (1992-11-01), Ohno et al.
patent: 5215472 (1993-06-01), DelPrete et al.
patent: 5221209 (1993-06-01), D'Amico
patent: 5362985 (1994-11-01), Ma et al.
patent: 5611654 (1997-03-01), Frattarola et al.
patent: 5702256 (1997-12-01), Severn
patent: 5713744 (1998-02-01), Laub
patent: 5905416 (1999-05-01), Shimid et al.
patent: 0 220 600 A2 (1987-05-01), None
patent: 1-110753 (1989-04-01), None
patent: 2-276995 (1990-11-01), None
patent: 8-185942 (1996-08-01), None
patent: 9-148018 (1997-06-01), None

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