Coating apparatus – Gas or vapor deposition – Work support
Reexamination Certificate
1998-12-17
2001-10-09
Nelms, David (Department: 2818)
Coating apparatus
Gas or vapor deposition
Work support
C118S500000, C118S72300R
Reexamination Certificate
active
06299693
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacture. More particularly, the present invention relates to a method and apparatus for aligning a wafer chuck in a semiconductor wafer processing device.
BACKGROUND OF THE INVENTION
The manufacturing of semiconductor devices typically includes hundreds of different process steps performed on a semiconductor wafer. The steps include creating circuit patterns, introducing dopants, and depositing films on a silicon wafer repetitively throughout the manufacturing process. These steps result in the formation of circuit elements such as transistors, capacitors and resistors that are interconnected to form electronic circuits. The circuits on a semiconductor wafer may be designed to do anything from controlling an elevator to running a laptop computer to monitoring the systems of an automobile.
Because the various circuit elements and interconnections that are built on a semiconductor substrate or wafer are built one on top of another in a sequential manner, it is important that each layer of the structure be substantially defect-free before the next layer is added. Otherwise, a defect in one layer may cause irreparable malfunctions in adjacent layers.
Defects are generally caused when unwanted particulate matter which is present during the manufacture of the semiconductor device comes to rest on and is incorporated into the layers of material being deposited on the semiconductor wafer. For example, a conductive particle placed in the wrong place may electrically connect or bridge two circuit elements on the substrate that are not supposed to be connected. This may disable the affected circuit elements or cause them to function improperly. Alternatively, an unwanted particle may disrupt a connection that is supposed to exist between two circuit elements, thereby preventing the circuit from operating properly.
Thus, for lithographic circuit forming techniques at the submicron level, where the wiring features or patterns are less than one micrometer in width, the size of contaminant particulate matter that must be controlled and eliminated is between about one fifth to one tenth of a micrometer. Preventing particles of such diminutive size from invading the semiconductor manufacturing procedure is obviously very difficult.
Contamination by unwanted particles can best be avoided if the sources of such contaminants are eliminated. There are two major sources of contaminant particles that may be introduced into a semiconductor manufacturing process. The first is the environment in which the semiconductor wafer is processed, i.e., the equipment in and with which the wafer is processed, the ambient air surrounding the wafer, and gases or fluids that are used for various processes performed on the wafer during manufacture. These contaminants that are external to the wafer can generally be kept away from the wafer by the proper use of filters, and other precautions that are commonly known.
The second source of particle contaminants is the wafer itself. As the wafer is processed, particulate matter may be released from the wafer by abrasion or breakage resulting from stresses imposed on the wafer during the manufacturing process. For example, a wafer may be clamped down or held along its edges by wafer clamps during some stages of processing. This abrasion of the edges can cause particulate matter to break free. The freed matter then becomes a contamination hazard.
A common approach for controlling the amount of breakage or peeling of particulate matter from the edge of a wafer has been to chamfer the edge. This chamfering or rounding of the edge of the substrate before the wafer is processed has been successful in reducing the release of particles that would otherwise be generated from the substrate edge itself.
Moreover, in some semiconductor processing, the edge of the wafer acquires an extra bulge of material that can more easily break free and result in contaminating particles. For example, when dielectric spin-on-glass (SOG) is spun on a wafer, it tends to form a bead as it advances towards the edge of the wafer. This results in a bulbous piling of material at the edge of the wafer which can be a source of contaminants in subsequent processing. Other layers that are added to a wafer by spin coating may cause similar edge beads.
Consequently, the extra material that accumulates on the edge of the wafer, the edge bead, is removed by grinding or etching the circumferential portion of the wafer. This tends to reduce contaminants originating from the wafer's edge.
One known process for removing the edge bead caused by spin coating involves rinsing the edge of the wafer with a solvent to dissolve the unwanted edge bead. This process is known as edge-bead rinsing (“EBR”). The solvent is washed over the edge of the wafer until the bead is removed. Subsequent processing may then continue.
In an edge bead rinsing process, wafers are delivered individually to the rinsing device on a pair of parallel transport belts. A wafer chuck then engages each wafer and lifts it into the rinsing device where the edge bead rinsing takes place. It is critical to the rising process that the chuck engage the center of the wafer. If the chuck does not engage the center of the wafer, the rinsing to remove the edge bead will be uneven. For example, material that is not supposed to be removed may be rinsed from the wafer while portions of the unwanted edge bead remain.
At present, there is no device or method known for easily and precisely aligning the wafer chuck so as to engage the center of a wafer as delivered by the transport belts. A technician generally must align the wafer chuck by simply eyeballing its placement with respect to the transport belts. Moreover, with use, the wafer chuck tends to lose its alignment. Consequently, the chuck must be realigned, for example, weekly.
Therefore, there is a need in the art for an apparatus and method for readily and accurately aligning the wafer chuck to engage the center of each wafer as it is delivered on the parallel transport belts.
SUMMARY OF THE INVENTION
Consequently, it is an object of the present invention to meet the above-described needs and others. Specifically, it is an object of the present invention to provide an apparatus and method for readily and accurately aligning the wafer chuck to engage the center of each wafer as it is delivered on the parallel transport belts. Additional objects, advantages and novel features of the invention will be set forth in the description which follows or may be learned by those skilled in the art through reading these materials or practicing the invention. The objects and advantages of the invention may be achieved through the means recited in the attached claims.
To achieve the stated and other objects, the present invention may be embodied and described as a tool for aligning a wafer chuck in an edge bead rinsing device. The tool is a substantially circular substrate having a size substantially equal to the semiconductor wafers to be processed in the edge bead-rinsing device. The substrate also has a recess on the underside that is centered with respect to the substrate and sized to receive therein the wafer chuck when the wafer chuck is correctly aligned.
The tool preferably also includes a hole drilled in the center of the substrate and rectangular slots cut in opposite sides of the substrate corresponding to transport belts for transporting semiconductor wafers. The tool may be made of polypropylene and ¼ inch thick. Alternatively, the tool may be made from Delrin.
The present invention also encompasses a method of aligning a wafer chuck of an edge bead rinsing device by placing a substantially round centering tool at an end of a semiconductor wafer transport path; and aligning the wafer chuck to engage the tool in a recess sized to receive the wafer chuck. More particularly, the method includes placing the tool against stops provided at the end of the transport path; and aligning the two rectangular slots cut
DeLuna, Jr. Roger
Kanozik, III Frank John
Ramirez Andres Roberto
Berry Renee R.
Kananen Ronald P.
Nelms David
Rader Fishman & Grauer
Sony Corporation
LandOfFree
Method and apparatus for aligning a wafer chuck in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for aligning a wafer chuck in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for aligning a wafer chuck in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2606161