Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-03-27
2002-02-12
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169300
Reexamination Certificate
active
06346931
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to field emission devices (“FEDs”). More specifically, the present invention relates to a method and an apparatus with the capability to adjust on-line image definition on FED screen displays.
BACKGROUND OF THE INVENTION
Currently, in the world of computers and elsewhere, the dominate technology for constructing flat panel displays is liquid crystal display (“LCD” technology and the current benchmark is active matrix LCDs (“AMLCDs”). The drawbacks of flat panel displays constructed using AMLCD technology are the cost, power consumption, angle of view, smearing of fast moving video images, temperature range of operation, and the environmental concerns of using mercury vapor in the AMLCD's backlight.
A competing technology is cathode ray tube (“CRT”) technology. In this technology area, there have been many attempts in the last 40 years to develop a practical flat CRT. In the development of flat CRTs, there has been the desire to use the advantages provided by the cathodoluminescent process for the generation of light.
The point of failure in the development of flat CRTs has centered around the complexities in the developing of a practical electron source and mechanical structure.
In recent years, FED technology has come into favor as a technology for developing low power, flat panel displays. FED technology has the advantage of using an array of cold cathode emitters and cathodoluminescent phosphors for the efficient conversion of energy from an electron beam into visible light. Part of the desire to use FED technology for the development of flat panel displays is that is very conductive for producing flat screen displays that will have high performance, low power, and light weight. Some of the specific recent advances associated with FED technology that have made it a viable alternative for flat panel displays are large area 1 &mgr;m lithography, large area thin-film processing capability, high tip density for the electron emitting micropoints, a lateral resistive layer, anode switching, new types of emitter structures and materials, and low voltage phosphors.
Referring to
FIG. 1
, a representative cross-section of a prior art FED is shown generally at
100
. As is well known, FED technology operates on the principal of cathodoluminescent phosphors being exited by cold cathode field emission electrons. The general structure of a FED includes silicon substrate or baseplate
102
onto which thin conductive structure is disposed. Silicon baseplate
102
may be a single crystal silicon layer.
The thin conductive structure may be formed from doped polycrystalline silicon that is deposited on baseplate
102
in a conventional manner. This thin conductive structure serves as the emitter electrode. The thin conductive structure is usually deposited on baseplate
102
in strips that are electrically connected. In
FIG. 1
, a cross-section of strips
104
,
106
, and
108
is shown. The number of strips for a particular device will depend on the size and desired operation of the FED.
At predetermined sites on the respective emitter electrode strips, spaced apart patterns of micropoints are formed. In
FIG. 1
, micropoint
110
is shown on strip
104
,micropoints
112
,
114
,
116
, and
118
are shown on strip
106
, and micropoint
120
is shown on strip
108
. With regard to the patterns of micropoints, on strip
106
,a square pattern of 16 micropoints, which includes micropoints
112
,
114
,
116
, and
118
, may be positioned at that location. However, it is understood that one or a pattern of more than one micropoint may be located at any one site.
Preferably, each micropoint resembles an inverted cone. The forming and sharpening of each micropoint is carried out in a conventional manner. The micropoints may be constructed of a number of materials. Moreover, to ensure the optimal performance of the micropoints, the tips of the micropoints can be coated or treated with a low work function material.
Alternatively, the structure substrate, emitter electrode, and micropoints may be formed in the following manner. The single crystal silicon substrate may be made from a P-type or an N-type material. The substrate may then treated by conventional methods to form a series of elongated, parallel extending strips in the substrate. The strips are actually wells of a conductivity type opposite that of the substrate. As such, if the substrate is P-type, the wells will be N-type and vice-versa. The wells are electrically connected and form the emitter electrode for the FED. Each conductivity well will have a predetermined width and depth (which it is driven into the substrate). The number and spacing of the strips are determined to meet the desired size of field mission cathode sites to be formed on the substrate. The wells will be the sites over which the micropoints will be formed. No matter which of the two methods of forming the strips is used, the resulting parallel conductive strips serve as the emitter electrode and form the columns of the matrix structure.
After either of two methods of forming the emitter electrode are used, dielectric insulating layer
122
is deposited over emitter electrode strips
104
,
106
, and
108
, and the pattern micropoints located at predetermined sites on the strips. The insulating layer may be made from silicon dioxide (SiO
2
).
A conductive layer is disposed over insulation layer
122
. This conductive layer forms extraction structure
132
. The extraction structure
132
is a low potential anode that is used to extract electrons from the micropoints. Extraction structure
132
may be made from chromium, molybdenum, or doped polysilicon or silicided polysilicon. Extraction structure
132
may be formed as a continuous layer or as a parallel strips. If parallel strips form extraction structure
132
, it is referred to as an extraction grid, and the strips are disposed perpendicular to emitter electrode strips
104
,
106
, and
108
. The strips when used to form extraction structure
132
, they are the rows of the matrix structure. Whether a continuous layer or strips are used, once either is positioned on the insulating layer, they are appropriately etched by conventional methods to surround but be spaced away from the micropoints.
At each intersection of the extraction and emitter electrode strips or at desired locations along emitter electrode steps when a continuous extraction structure is used, a micropoint or pattern of micropoints are disposed on the emitter strip. Each micropoint or pattern of micropoints are meant to illuminate one pixel of the screen display.
Once the lower portion of the FED is formed according to either of the methods described above, faceplate
140
is fixed a predetermined distance above the top surface of the extraction structure
132
. Typically, this distance is several hundred &mgr;m. This distance is maintained by spacers that are formed by conventional methods and have the following characteristics: (1) non-conductive to prevent an electrical breakdown between the anode (at faceplate
140
) and cathode (at emitter electrodes
104
,
106
, and
108
), (2) mechanically strong and slow to deform, (3) stable under electron bombardment, (4) order of 400° C., and (5) small enough not to interfere with the operation of the FED. Representation spacers
136
and
138
are shown in FIG.
1
.
Faceplate
140
is a cathodoluminescent screen that is constructed from clear glass or other suitable material. A conductive material, such as indium tin oxide (“ITO” is disposed on the surface of the glass facing the extraction structure. ITO layer
142
serves as the anode of the FED. A high vacuum is maintained in area
134
between faceplate
140
and baseplate
102
.
Black matrix
149
is disposed on the surface of the ITO layer
142
facing extraction structure
132
. Black matrix
149
defines the discreet pixel areas for the screen display of the FED. Phosphor material is disposed on ITO layer
142
in the appropriate areas defined by black matrix
149
. Representative pho
Cathey David A.
Cathey James J.
Frenel Vanel
Hale and Dorr LLP
Micro)n Technology, Inc.
Shalwala Bipin
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