Method and apparatus for adjusting the phase and frequency...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

Reexamination Certificate

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C327S248000, C327S276000

Reexamination Certificate

active

06777993

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of frequency generation devices such as clocking devices in electrical systems. More specifically, the present invention relates to a method and apparatus for adjusting the phase and frequency of a periodic wave.
BACKGROUND OF THE INVENTION
In applications such as plesiochronous or isochronous telecommunication systems, it is desirable to make adjustments to the phase of a clock in order to synchronize the clock with an external reference. It may also be necessary in these applications to generate a positive or negative frequency adjustment to the clock. The phase and frequency adjustments may be accomplished by periodically adjusting the phase of the clock by advancing or retarding the phase of the clock.
In the past, analog circuits such as phase locked loops, mixers and other electrical circuits having inductors and capacitors were used to offset the frequency and phase of a clock. These analog circuits adjusted the phase and frequency directly or smoothed out phase discontinuities by adding or dropping clock pulses. A second approach used in the past to provide a clock with a phase and frequency matching an external reference was to synthesize a clock with the desired phase and frequency characteristics of the external reference. This was achieved by dividing an internal clock operating at a higher speed clock. By changing the modulus of the divider, the phase or frequency of the synthesized clock could be adjusted. Both these approaches, however, suffered from various drawbacks. The analog circuits used to offset the frequency and phase of a clock could not be constructed using digital circuit components. In order to implement the analog circuits, special design consideration had to be given to the placement of the circuit components. Alternatively, the analog circuits had to be placed off-chip. The approach of synthesizing a clock with the desired phase and frequency characteristics of the external reference required a clock operating at a much higher frequency than the external reference. Implementing a high speed clock was difficult and costly.
Thus, what is needed is an efficient and effective method and apparatus for adjusting the phase and frequency of a period wave.
SUMMARY
According to an embodiment of the present invention, a phase vernier is implemented using a chain of logic components. A phase and frequency of a periodic wave inputted into the phase vernier may be adjusted by selecting an inject input of a logic component and setting the logic component to an inject mode. The phase vernier may operate to add or delete integral half-cycles or full-cycles of the periodic wave to permit unlimited phase adjustments. The phase vernier may be implemented using digital logic circuits which allow it to be more easily integrated into an electronic system. The phase vernier may operate to adjust the phase and frequency of a periodic wave without requiring the period wave to be generated using a high speed clock.
A delay circuit is disclosed according to an embodiment of the present invention. The delay circuit includes a phase vernier having a plurality of logic components. Each of the logic components has a selectable inject input capable of adjusting a phase of an input of the phase vernier.
A method for adjusting a phase of an input using a delay circuit is disclosed according to a first embodiment of the present invention. The phase is advanced by setting a logic component in a last stage of the delay circuit to an inject mode. Forward wrapping is performed. The phase is further advanced by setting a logic component in a stage subsequent to a secondary injection point to the inject mode.
A method for adjusting a phase of an input using a delay circuit is disclosed according to a second embodiment of the present invention. The phase is retarded by setting a logic component in a first stage of the delay circuit to an inject mode. Backward wrapping is performed. The phase is further retarded by setting a logic component in a stage prior to a secondary injection point to the inject mode.


REFERENCES:
patent: 5838755 (1998-11-01), Tammelin
patent: 6037812 (2000-03-01), Gaudet
patent: 6104223 (2000-08-01), Chapman et al.

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