Method and apparatus for adjusting PLL and/or DLL timing...

Details Method and apparatus for adjusting PLL and/or DLL timing... Method and apparatus for adjusting PLL and/or DLL timing...

2011-06-07

2011-06-07

Cho, James H. (Department: 2819)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S017000, C331S17700V, C327S157000, C327S158000

Reexamination Certificate

active

07956693

ABSTRACT:
A method and apparatus for adjusting PLL and/or DLL timing offsets have been disclosed.

REFERENCES:
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patent: 6542040 (2003-04-01), Lesea
patent: 6608530 (2003-08-01), Green et al.
patent: 6801028 (2004-10-01), Kernahan et al.
patent: 6867627 (2005-03-01), Murtagh
patent: 6985705 (2006-01-01), Shohara
patent: 7187220 (2007-03-01), Alben et al.

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