Method and apparatus for adjusting load impedance of a...

Details Method and apparatus for adjusting load impedance of a... Method and apparatus for adjusting load impedance of a...

2011-02-01

2011-02-01

Jones, Stephen E (Department: 2817)

Wave transmission lines and networks

Coupling networks

With impedance matching

C333S033000

Reexamination Certificate

active

07880558

ABSTRACT:
The application discloses a method and apparatus for adjusting internal load impedances, by section, at feed points present on a distributed amplifier's output transmission line. The method includes determining a summing-point load impedance (Zx) at an off-chip output transmission line of the distributed amplifier. The method further includes determining a driving-point load impedance (Zd) at an output of an on-chip power transistor. The driving-point load impedance diverges and disperses over frequency from that summing-point load impedance due to reactance of at least one on-chip component coupled to the output of the on-chip power transistor. The method then includes determining and providing an offset to summing-point load impedance (Zx) based on the driving-point load impedance (Zd) such that the driving-point load impedance (Zd) converges to the summing-point load impedance (Zx) of that distributed amplifier section.

REFERENCES:
patent: 5920230 (1999-07-01), Beall
patent: 6597242 (2003-07-01), Petz et al.
patent: 6614307 (2003-09-01), Zhao et al.
patent: 7173502 (2007-02-01), Hosoya et al.
patent: 7706756 (2010-04-01), Sato et al.
Related PCT/US2009/053321—International Search Report with Written Opinion mailed Mar. 22, 2010—10 pages.

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