Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
1998-10-05
2001-10-16
Eisenzopf, Reinhard J. (Department: 2614)
Television
Synchronization
Automatic phase or frequency control
C348S536000, C348S571000, C348S538000
Reexamination Certificate
active
06304296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique of adjusting a dot clock signal for processing a video signal. Especially the invention pertains to a technique of adjusting the phase of a dot dock signal as well as to a technique of adjusting the frequency of the dot clock signal. The video signal in the present invention denotes an image signal supplied from an image signal output device such as a personal computer.
2. Description of the Related Art
FIG. 40
is a block diagram illustrating a video image display apparatus utilizing a conventional technique. The video image display apparatus includes an A-D converter
1
, a driving circuit
2
, a display device
3
, a display timing control circuit
5
, a PLL (Phase Locked Loop) circuit
7
, and a delay circuit
10
. The PLL circuit
7
multiplies the frequency of a horizontal synchronizing signal
102
for an analog video signal
101
, by a predetermined factor Nd to generate a reference clock signal
200
. The delay circuit
10
gives a delay &phgr; to the reference clock signal
200
to generate a dot clock
201
. The analog video signal
101
is sampled by an A-D converter
1
at a rise of the dot clock
201
and converted to a digital video signal
110
. The driving circuit
2
executes a signal processing on the digital video signal
110
to make it suitable for the display device
3
, and supplies the processed video signal to the display device
3
for display of an image. The dot clock
201
is also given to the driving circuit
2
, the display device
3
, and the display timing control circuit
5
. The display timing control circuit
5
further receives the horizontal synchronizing signal
102
. The display timing control circuit
5
controls the display timing of the display device
3
according to the horizontal synchronizing signal
192
and the dot clock
201
.
The PLL circuit
7
and the delay circuit
10
constitute a dot clock regeneration circuit for regenerating a dot clock signal (dot clock) suitable for the processing of the analog video signal
101
, from the horizontal synchronizing signal
102
. The factor Nd in the PLL circuit
7
and the delay &phgr; in the delay circuit
10
are adjustable parameters in generating the dot clock
201
. In other words, it is desirable to set appropriate values to both the delay &phgr; and the factor Nd, in order to regenerate the dot clock signal suitable for the analog video signal
101
. The delay &phgr; of the dot clock signal relates to the phase of the dot clock signal, whereas the factor Nd relates to the frequency of the dot clock signal. There are some problems regarding the adjustment of the delay &phgr; (that is, the adjustment of the phase) and the adjustment of the factor Nd (that is, the adjustment of the frequency) as described below.
The analog video signal
101
output from a video image output apparatus, such as a personal computer, was generated in synchronism with an internal video clock of the video image output apparatus. The signal level thus varies at the cycles of the internal video clock. A dot clock (also referred to a sampling clock) having the same frequency as that of the internal video clock of the video image output apparatus is required in order to carry out appropriate signal processing for displaying a video image corresponding to the analog video signal
101
on the display device
3
or the signal processing for writing the analog video signal
101
into a memory. In the computer system, such as a personal computer, however, no video clock is output to an output terminal of video signals. In the conventional system shown in
FIG. 40
, the PLL circuit
7
multiplies the frequency of the horizontal synchronizing signal
102
by the factor Nd to generate the reference clock signal
200
, and the delay circuit
10
further gives a delay to the reference clock signal
200
to regenerate the dot clock
201
Here the factor Nd in the PLL circuit
7
is set to coincide with a demultiplication factor, or frequency division ratio, used for generating the horizontal synchronizing signal
102
from the video clock in the video image output apparatus. This makes the dot clock
201
to have the same frequency as that of the original video clock.
FIGS.
41
(
a
)-
41
(
c
) are timing charts showing the relationship between the video signal
101
and the dot clock
201
. The video signal
101
has a stable range
121
having image information proper to the video signal
101
and a transient range
122
including ringing and rounding generated by the effects of an output circuit of the video image output apparatus and a connection cable. When a dot clock rising in the stable range
121
such as a dot clock
201
A shown in FIG.
41
(
b
) is used, a normal video image is displayed on the display device
3
. When a dot clock rising in the transient range
122
such as a dot clock
201
B shown in FIG.
41
(
c
) is used, on the other hand, the A-D converter
1
samples image information that is not proper to the video signal
101
, and the resulting video image displayed on the display device
3
accordingly has undesirable noises or poor sharpness.
FIGS.
42
(
a
)-
42
(
c
) are timing charts showing the relationship between the horizontal synchronizing signal
102
, the reference clock
200
, and the dot clock
201
. The reference clock
200
output from the PLL circuit
7
is in phase with the horizontal synchronizing signal
102
. Since the relationship between the phase of the horizontal synchronizing signal
102
and that of the video signal
101
is not specifically defined, the phase at a rise of the reference clock
200
may deviate from the phase of the video signal
101
. A rise of the dot clock
201
may accordingly exist in the transient range
122
(FIG.
41
(
a
)).
In the conventional system, a user manually adjusts the delay time &phgr; (that is, the phase) of the dot clock
201
shown in FIG.
42
(
c
) to an optimum state while checking a video image on the display device
3
so that the displayed video image has no noise and sufficient sharpness. This manual operation is, however, rather troublesome, and little understanding of the requirement for the adjustment may lead to some misunderstanding that the display device has poor performance or even malfunctions.
A method of automatically adjusting the phase of the dot clock
201
is, for example, disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 4-276791. This method comprises the steps of sampling two sets of image data in synchronism with dot clocks having different phases; storing them into two different memories; and determining an optimum phase of the dot clock so that the two sets of image data read out of the memories coincide with each other. When the video signal includes ringing and rounding and has a narrow stable range, only a little shift of the phase causes a difference in the resulting image data. Potential noise also slightly changes the image data. The two sets of image data obtained with the dot clocks with different phases thus hardly coincide with each other actually, and it is rather difficult to determine the optimum phase of the dot clock. This method also requires two high-speed line memories to process high-speed video signals, thereby undesirably raising the equipment cost.
The adjustment of the factor Nd in the PLL circuit
7
(FIG.
40
), that is, the adjustment of the frequency of the dot clock, also has the following problem.
FIG. 43
shows timing of the video signal
101
in a two-dimensional manner. A standard video signal is a one-dimensional signal representing a video image on each scanning line. One page image is constructed by scanning each line from left to right in the horizontal direction and repeating the scanning procedure for all the lines in one page from an upper left end to a lower right end. A horizontal synchronizing signal
102
adjusts the scanning timing of the video signal
101
in the horizontal direction, whereas a vertical synchronizing signal
103
adjusts the scanning timing of the
Eisenzopf Reinhard J.
Lo Linus H.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Seiko Epson Corporation
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