Method and apparatus for addressing and testing more than two AT

Details Method and apparatus for addressing and testing more than two AT Method and apparatus for addressing and testing more than two AT

1996-05-02

1997-07-01

Beausoliel, Jr., Robert W.

Excavating

395427, 371 211, 304239, 3042217, 3042384, 361685, G06F 1100

Patent

active

056447051

ABSTRACT:
A method and apparatus for addressing a plurality of AT Attachment, Integrated Drive Electronics (ATA/IDE) disk drive assemblies from a single PC/AT thereby allowing the performance of manufacturing tests on multiple IDE drives using the ISA bus. Other drive assemblies are address during the substantial PC/AT CPU and I/O idle time available during the testing of a selected drive assembly. The system includes a PC/AT computer having an ISA bus, a plurality of ATA/IDE disk drives, and a multi-master card disposed between the PC/AT and the plurality of disk drives. The multi-master card includes an IDE controller card with a parallel port. Signals are generated to select one of the plurality of disk drives and ISA bus signals are routed to the selected disk drives. All the disk drives are disabled but the selected disk drive and a three bit signal line is used to select the disk drive for testing. Test capabilities are provided for in a standard, local, and remote mode of operation. The addressing scheme allows all drives to be addressed as master drives and each master on the bus can have a slave attached.

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