Method and apparatus for addressing a peripheral interface by ma

Details Method and apparatus for addressing a peripheral interface by ma Method and apparatus for addressing a peripheral interface by ma

1982-04-29

1985-08-13

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 304

Patent

active

045354049

ABSTRACT:
A method and apparatus for addressing a peripheral interface by mapping into the memory address space of a processor contained in a peripheral controller. The processor in the peripheral controller initializes interface logic within the peripheral controller and in the host system peripheral interface logic to which the peripheral controller is attached to either transmit or receive a block of data. Once initialized, units of data are transmitted across the interface between the peripheral controller and host system using a strobe and acknowledge signal to indicate when data can be taken or placed on data lines. The processor is placed in a wait state as each unit of data is transferred and a watch dog timer is provided to detect any transfer that is not completed within the normal response time of the interface.

REFERENCES:
patent: 4124888 (1978-11-01), Washburn
patent: 4131945 (1978-12-01), Richardson et al.
patent: 4156932 (1979-05-01), Robinson et al.
patent: 4365296 (1982-12-01), Ulmer
patent: 4456970 (1984-06-01), Catiller et al.
Digital pdpll Handbook, copyrighted 1969, (pp. 46 to 51).
Intel, Component Data Catalog, 1979, (pp. 9-54 to 9-69).
MC68120/MC68121, Intelligent Peripheral Controller User's Manual, Motorola Inc., pp. 1-1 to 1-12, 1981.

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