Method and apparatus for addressing a memory by array transforma

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G06F 1200

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active

048191523

ABSTRACT:
A memory having an address generator which generates nested address sequences specified by an array transformation operator in a programmable processor, thereby allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a complex present instruction. The address generator generates row and column indices specified by the array transformation operator comprising an initial reference point parameter, a boundary parameter and a plurality of displacement and length parameters expressed relative to the initial reference point. Address sequences for data representing a vector, matrix, or block are generated in a single memory in accordance with the factored series of nested addressing sequences specified by the array transformation.

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