Method and apparatus for addressing a digital memory

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123 32EA, 364900, G06F 1520, F02D 500

Patent

active

041077172

ABSTRACT:
A central digital memory contains data relating values of operational variables of an installation to values of a stored parameter. The central memory is addressed in parallel via input lines carrying the address of the stored data. The address is generated by selecting one of several discrete input lines leading to an address selector memory which contains preliminary addresses related to the various operational states of the installation. A portion of the preliminary address is delivered directly to the central memory whereas another portion is used to preset a counter. If the particular operational state is dependent on another parameter, for example temperature, a temperature-dependent clocking frequency is admitted to the counter and alters its contents which are then used to supplement the first portion of the address already delivered to the central memory. If no temperature dependency exists, the second portion of the address is passed on without change.

REFERENCES:
patent: 3816717 (1974-06-01), Yoshida et al.
patent: 3838397 (1974-09-01), Watson et al.
patent: 3846625 (1974-11-01), Sasayama
patent: 3904856 (1975-09-01), Monpetit
patent: 3909601 (1975-09-01), Yamawaki et al.

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