Patent
1996-09-12
1998-09-29
Teska, Kevin J.
G06F 9455
Patent
active
058156860
ABSTRACT:
A method and a system for address space translation. The present invention is implemented on a computer system having a microprocessor with a translation look aside buffer (TLB). The address space translation system of the present invention translates an emulated virtual address space into a physical address space. The system receives a virtual address from a process running on the system. The system compares the TLB with the virtual page number of the virtual address and returns a physical page number from the TLB when there is a match in the TLB with the virtual page number. When there is not a match, the system determines whether the virtual address is an emulated virtual address or a native virtual address. If the virtual address is an emulated virtual address, the system translates the emulated virtual address to a corresponding physical address. The system then stores the virtual page number from the emulated virtual address and the corresponding physical page number in the TLB.
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Earl William J.
Mesard Wayne Stuart
Fiul Dan
Silicon Graphics Inc.
Teska Kevin J.
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