Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-04-07
2001-09-25
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
Reexamination Certificate
active
06295517
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the simulation of digital electronic circuits which have been described at a register transfer level. More specifically, the present invention relates to determining the most efficient mode for simulating clusters of a circuit description.
BACKGROUND OF THE INVENTION
To tackle the increasing complexity of digital electronic circuits, designers need faster methods of simulating such circuits, particularly in light of ever-shrinking product development times.
The complexity of designing such circuits is often handled by expressing the design in a high-level hardware description language (HDL) such as Verilog.
High-level HDLs allow the designer to save design time by permitting him or her to express the desired functionality at the register transfer level (RTL) of abstraction or higher. The high-level HDL description is then synthesized into an actual circuit through a process, well known to those of ordinary skill in the art, of translation and optimization.
High-level HDLs describe, directly or indirectly, the two main kinds of circuit entities of an RTL circuit description: i) state devices or sequential logic which store data upon application of a clock signal, and ii) combinational logic. The state devices typically act as either: i) an interface between conceptually distinct circuit systems, or ii) storage for the results of functional evaluation performed by the combinational logic.
In order to verify the functionality of such high-level HDL descriptions, it is usually desirable to simulate the circuit thereby produced before actually manufacturing it.
Simulation can occur at a variety of levels of modeling abstraction. Known example levels of modeling abstraction are: transistor, gate, register transfer and behavioral. Typically, the lower the level of abstraction, the more accurate the simulation. Typically, however, the lower the level of abstraction the greater is the amount of time required to perform the simulation.
Simulation time can be a significant limitation upon a designer's ability to explore a variety of design alternatives and therefore it is almost always desirable to achieve a simulation time which is as short as possible.
Conventional simulators assume that the level of simulation activity, throughout a design to be simulated, is uniform. Simulation activity is determined by the rate at which signal levels, within circuit elements being simulated, change. If the level of activity is assumed to be uniformly low, then it is desirable to simulate using an event-triggered mode in which evaluation is performed only for those circuit elements whose signal levels are changing. Alternatively, if the level of activity is assumed to be uniformly high, then it is desirable to simulate using an oblivious cycle-based mode in which all circuit elements are evaluated upon every clock cycle since the scheduling overhead inherent in any event-triggered approach is avoided.
However, typical designs have non-uniform activity levels due to their components having different characteristics. Examples of different types of components, each of which is often associated with a different level of simulation activity, are: controller unit, datapath unit, memory unit and input/output unit.
Therefore, certain regions of a digital electronic system may have high levels of simulation activity, while other regions of the system may have low levels of activity.
SUMMARY OF THE INVENTION
The present invention is addressed to a simulation architecture in which a circuit designer proceeds according to the following major steps: i) an input circuit description to be simulated is compiled into an initial circuit compilation, ii) part of the complete suite of test vectors, such portion being known as the profile test vector subset, is simulated upon the initial circuit compilation to produce activity data, iii) the input circuit description to be simulated is compiled again, but is optimized utilizing the activity data, and iv) the optimized circuit compilation is simulated with the full suite of test vectors.
The present invention is addressed to RTL simulation and any circuit description from which an RTL netlist can be inferred can be used as input.
The first major step of initial circuit compilation proceeds as follows. The input circuit description is translated into an initial RTL network representation including sequential and/or combinational objects. Next, translation of the RTL network into a network of clusters is accomplished. In general, a cluster is a region of the circuit which has uniform characteristics. The identification of clusters operates as follows. The program starts at a register (or state device) in the RTL network and for each of its inputs traces the fanin. The cluster thereby produced comprises a register and all of the traced fanin combinational circuitry driving its inputs. As discussed below, certain conditions occurring during the tracing can also lead to the creation of clusters composed entirely of combinational circuitry.
The initial clustering process, by default, chooses a simulation mode for all clusters that is known as event-triggered cycle-based (defined below). The other possible simulation mode for a cluster, in accordance with the present invention, is oblivious-triggered cycle-based (defined below).
The next (and second) major step in utilizing the simulation architecture, as discussed above, is to simulate the object code produced by the initial circuit compilation upon a portion of the complete suite of test vectors, such portion being known as a Profile Test Vector Subset file, to produce an Activity Data file containing simulation activity data regarding each individual cluster. This is possible because the initial circuit compilation includes additional object code which causes it to output the simulation activity of its clusters.
In the third major step of utilizing the simulation architecture, the designer again compiles the circuit to be simulated, but this compilation is optimized utilizing the Activity Data file. As part of the process of producing the optimized compilation, a Profile Analyzer must be run upon the Activity Data file. The Profile Analyzer takes the Activity Data file as input, calculates the simulation activity of each cluster and based upon the simulation activity produces as output a Cluster Directives file that indicates which clusters (all of which are event-triggered cycle-based by default) can either be merged into larger event-triggered cycle-based clusters or individually switched from an event-triggered cycle-based simulation mode to an oblivious-triggered cycle-based simulation mode. The Cluster Directives file is read by another program, known as Adaptive Clustering, as part of the optimized compilation to produce a network of clusters in which the evaluation mode has been chosen, or clusters have been merged, on a cluster-by-cluster basis, to optimize simulation efficiency (and therefore minimize simulation time).
The event-triggered cycle-based mode is more efficient than oblivious-triggered cycle-based if the simulation activity of the cluster is low. Oblivious-triggered cycle-based is more efficient than event-triggered cycle-based if the simulation activity of the cluster is high.
Therefore, if the simulation activity of a cluster is low, the Profile Analyzer will not produce a directive and therefore leave the cluster as event-triggered cycle-based. If the simulation activity of a cluster is high, the Profile Analyzer will produce a directive for the Cluster Directives file causing the cluster's mode of simulation to switch to oblivious-triggered cycle-based. If the simulation activity of a cluster is medium (between high and low), then the Profile Analyzer will leave the cluster as event-triggered cycle-based but will produce a directive for the Cluster Directives file marking it as a candidate for merging. The Adaptive Clustering program will then seek to merge all candidates for merging.
The optimized compilation, resulting from
Kuchlous Alok
Malpani Sanjay
Roy Arnob
Brown & Raysman Millstein Felder & Steiner LLP
Jones Hugh
Kaplan Jonathan T.
Synopsis, Inc.
Teska Kevin J.
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