Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
1999-03-01
2002-04-23
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S079000, C702S117000, C702S123000
Reexamination Certificate
active
06377901
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to automated testing techniques, and, more particularly, to a method for adaptively learning test measurement delays on an individual device test for the purpose of reducing the total device test time.
BACKGROUND OF THE INVENTION
Automated equipment is used to perform a wide variety of tasks that might otherwise be performed manually at a slower rate and/or greater cost. Automation of a task typically incurs the overhead of a systematic delay before each performance of the actual task due to systematic delays in the automated equipment as it seeks a ready state. For example, in the large-scale production of electronic circuits, automated test equipment is used for setting up and performing tests on each circuit board of a run of circuit boards. A run is a testing sequence of the same type of assembly with no intervening different types of assemblies. A typical automated circuit tester includes a measurement circuit, a bed-of-nails fixture, and a set of programmable relay matrices and internal measurement busses. When testing a circuit under test, the circuit under test is seated on the fixture, which probes nodes of the component under test. Before measurements may be safely obtained without risk of any errors in the measurements due to the tester itself, the automated circuit tester must achieve a ready state in which all desired measurement paths and associated components are fully operational and in the correct position or configuration. Typically, automated testers include multiple components that must be configured and/or waited upon before the tester can be guaranteed to be in a ready state to perform the actual task at hand. Often there exists no method of determining whether a given tester component is in a ready state. For example, in a tester that comprises a programmable relay matrix, there is an inherent delay caused by the programming of the matrix followed by a delay caused by the actuation of each of the relays. Because no method exists for visually or otherwise determining whether a relay has opened or closed, a typical tester will wait the maximum rated delay time for the relay as specified by the relay manufacturer. If the relay open/close actuation wait times are anything less than the specified maximum relay open/close actuation times, incorrect measurements could occur due to incomplete connections (i.e., relays not yet being closed when the measurements are made). Because the actual actuation time of the slowest operating relay component in the tester may in fact be far less than the maximum specified actuation time, the test time overhead due to the systematic delay of the tester is greater than it need be, thereby yielding less production efficiency than achievable. In the testing of a long run of boards, the systematic delay overhead can add up to a significant amount of lost time. In addition, even though the test system is being set up in parallel with the relay open/close times, as coding techniques, software compilers, and native controllers improve in speed, the dominant time spent in making a simple component under test measurement will be waiting for the interconnect relays to physically open/close. As a result, the measurement test time is governed by the physical connection of the circuit under test to the measurement instruments.
Accordingly, a need exists for a system and method for adaptively learning the systematic delays of an automated tester in order to reduce the total testing time.
SUMMARY OF THE INVENTION
The present invention improves over prior art circuit automated testing techniques in several ways. The invention can be used to adapt to systematic delays in setting up the test configuration circuit, including delays in tester components lying in the measurement paths such as relay actuation times, achieving a steady state after turning on a DC power source, and any other type of delay that occurs between the initiation of the test configuration circuit setup until the test configuration circuit is in a ready state to allow measurements of a component under test to be taken.
In accordance with the method of the invention, the measurement delay times associated with executing a test on an automated tester are adaptively learned by setting a current delay time to an initial delay value, waiting the current delay time, and executing the test in which measurements are obtained by the automated tester. A determination is made based on the measurements as to whether the test passed or failed. If the test fails, because it may be due to a “false failure” condition due to the current delay time not having been long enough for the automated tester to have achieved a ready state, the current delay time is then reset to a different delay time, and the test is reexecuted after waiting the different delay time. In the preferred embodiment, the different delay time is set to the maximum specified delay time as specified by the component manufacturer for the slowest component that lies in the measurement paths in order to ensure that if the test fails after a retry, that the failure is not due to incomplete measurement path connections or the tester not having yet achieved a ready state when the measurements are taken.
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Adaptive Test Timing Characterization, Dec. 1984, IBM Technical Disclosure Bulletin, vol. 27, Issue 7A, pp. 3835-3838.
Crook David T.
List Steven K
Agilent Technologie,s Inc.
Barbee Manuel L.
Hoff Marc S.
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