Method and apparatus for adaptive timing optimization of an...

Details Method and apparatus for adaptive timing optimization of an... Method and apparatus for adaptive timing optimization of an...

2006-03-28

2006-03-28

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

C716S030000, C716S030000

Reexamination Certificate

active

07020589

ABSTRACT:
An optimization apparatus and method optimizes a functional block within a netlist of an integrated circuit design. A corresponding delay value is assigned to each of a plurality of pins of the block. Each pin corresponds to a respective signal path through the block. The delay values together form a delay value combination, which is selected from a continuous set of possible combinations in which each combination in the set satisfies a predetermined criteria. A circuit configuration for the block is then generated with a plurality of logic cells that are interconnected in the netlist such that the respective signal paths have delays through the block that are based on the corresponding delay values.

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