Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1997-04-24
2001-11-13
Olms, Douglas (Department: 2661)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S381000, C711S101000, C710S052000
Reexamination Certificate
active
06317427
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a buffer device and methods for adaptively sharing memory area among a plurality of functions, for example as provided between a transmit buffer and a receive buffer on a communications network switch.
2. Description of the Prior Art
FIG. 1
is a block diagram of an exemplary network switch
10
, which includes a network switch fabric
12
, six input/output ports
14
A-F, and six buffering and control circuits
16
A-F. Each buffering and control circuit
16
is coupled between the switch fabric
12
and a corresponding one of the ports
14
A-F. A network switch may have any number of ports, and may have its buffering and control functions either centralized, or distributed as shown in FIG.
1
. In operation, data is received on one of the ports (e.g., port
14
A) and a first corresponding buffering and control circuit (e.g.,
16
A) routes the communication data through the switch fabric
12
to a second buffering and control circuit (e.g.,
16
D) and to a second port (e.g.,
14
D).
FIG. 2
illustrates one known approach of buffering in a portion
20
of a communications network switch. A network port
24
is shown, coupled to the network switch fabric
22
via both receive buffer
26
and transmit buffer
28
. Control circuitry for the port
24
is not shown. In this example, buffering for the port
24
is achieved by using physically separate memory devices, one for transmit (28) and the other for receive (26). This approach allows a designer of a network switch to maximize buffering in both transmit and receive directions for a given memory density, and achieve a minimum latency in accessing the data. It does, however, have a drawback in cost and port density—i.e., two buffer devices are required per port on the printed circuit board (PCB), making the PCB design more complex because of the additional real estate requirement, which in turn raises the cost. Another drawback is that when more devices are added for buffering, less room is available for actual network ports on the PCB.
FIG. 3
illustrates another approach to switch buffering for a portion
30
of a network switch, in which a single buffering device
35
is coupled between the network switch fabric
32
and a network port
34
. A boundary
38
splitting the memory
34
in half (between transmit
37
and receive
36
) is static; the boundary may be predetermined by PCB hardware, or may be predetermined by software. An advantage of this approach (over the design shown in
FIG. 2
) is that by using only one buffer device per port, the PCB design is simplified, and generally the cost lower. One disadvantage is that buffering is reduced to half of the amount provided by the technique shown in
FIG. 2
, assuming both designs use the same memory device. Thus, for the single memory device
34
to achieve the same level of buffering as buffers
26
and
28
of
FIG. 2
, twice as many devices would be needed, eliminating the advantage.
In yet another buffering scheme, a switch includes a mechanism which selects buffering to the predetermined highest load data stream, at the expense of any data stream having a lesser load. For example, it may be predetermined that twice as much receive buffering as transmit buffering, is desirable. Such a design based on the
FIG. 2
embodiment would include a memory chip for the receive data that is twice the size of the memory chip used for the transmit data. To achieve the same result from the
FIG. 3
embodiment, the boundary
38
would dedicate ⅔ of the device to receive data, and ⅓ to transmit data.
A significant disadvantage results from all of these prior approaches because an individual port in a network switch seldom requires transmit buffering and receive buffering simultaneously. Accordingly, when receive buffering is required, the memory dedicated to transmit buffering represents unused resources. The same is true when transmit buffering is required, but receive buffering is not. Thus, there is a basic inefficiency in the prior art designs.
There is another disadvantage with the switch that weights the buffer towards the direction of the predetermined higher load data stream. Data networks, by their very nature, are extremely non-deterministic, and thus it is difficult to determine what type of traffic will be generated when a device is introduced at a large number of different customer sites. If a memory boundary is placed in a less than optimal position with respect to how the port will utilize the buffer, there is a possibility that memory will be required but unavailable for a data stream in one direction, and memory will be available but not required for a data stream traveling in the other direction.
Thus, a need arises for an improved memory device and method of buffering data.
SUMMARY OF THE INVENTION
A buffer device in accordance with one embodiment of the invention, automatically allocates a portion of a shared buffering (storage) area to a direction in which data buffering is required. This feature enables use of fewer parts in a hardware network device, which in turn lowers the cost, simplifies the design, and utilizes existing memory in a more efficient manner.
According to a method embodiment, a first memory area is allocated to buffering of a first port of a network switch, a second memory area is allocated to buffering of a second port of the network switch, and a third area is allocated as being a shared storage for buffering of the first port and buffering of the second port.
The above-described device and method take advantage of the common situation in which a single port in a network subsystem seldom requires simultaneous buffering for data being transmitted and data being received. In contrast, current network hardware designs provide separate storage buffers for transmit and receive data. The Adaptive Port Buffering (APB) scheme of this invention allows a single memory area to be used for both transmit and receive data. At least one version of the technique assumes some minimum amount of storage area dedicated for transmit and receive buffering, and a large common area that both can use as necessary, then relinquish when no longer needed.
Another embodiment is directed to a method for using storage area within a buffer device. The method comprises the steps of: storing data in a portion of the buffer device; determining a last written location of the buffer device; reading at least part of the data from the portion of the buffer device; determining a last read location of the buffer device; determining whether a predetermined amount of space is available in the portion of the buffer device based upon the last read location; and when a predetermined amount of space is available, using at least some of the predetermined space to store new data received, and when the predetermined amount of space is not available, increasing an amount of the buffer device to be used as the storage area to a new amount and storing the new data received in the new amount.
In accordance with another aspect of the invention, an electronic data storage circuit comprises a first storage area of a first size, a second storage area of a second size, and a control circuit, coupled to the first storage area and the second storage area, the control circuit having an output that increases the size of the first storage area to a provide more storage space to a function that uses the first storage area.
In any of the above embodiments, a portion of a third buffer may be assigned to a first buffering function based upon a need for more buffering space by the first buffering function. Additionally, at least part of the third buffer area portion may be assigned to a second buffering function based upon a need for more buffering space by the second buffering function. Moreover, the need for more buffering space may be determined by detecting that less than a predetermined amount of currently unused space is available within a designated buffer area.
Still further, a first buffering function may use a
Augusta Stephen D.
Brown Benjamin J.
Burgess James E.
Cabletron Systems Inc.
Olms Douglas
Pizarro Ricardo M.
Wolf, Greenfeld & Sacks, P.C.
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