Method and apparatus for adaptive memory access

Details Method and apparatus for adaptive memory access Method and apparatus for adaptive memory access

1994-06-30

1996-10-15

Kim, Matthew M.

395432, 395882, 395550, G06F 1200, G06F 112

Patent

active

055663257

ABSTRACT:
A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

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