Method and apparatus for adaptive delay cancellation in...

Details Method and apparatus for adaptive delay cancellation in... Method and apparatus for adaptive delay cancellation in...

2007-06-05

2007-06-05

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

10997236

ABSTRACT:
A phase locked loop (PLL) clock divider is provided that, in one implementation, includes a divider and a delay locked loop. The divider is operable to divide a reference clock signal and generate a divided clock signal. The divided clock signal has a different frequency relative to the reference clock signal. The delay locked loop is operable to substantially align the divided clock signal to the reference clock signal.

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IEEE Computer Society, “IEEE Standard for Information Technology—Telecommunications and Information Exchange Between Systems—Local and Metropolitan Area Networks—Specific Requirements—Part 3: Carrier Sense Multiple Access with Collision Detection(CSMA/CD)Access Method and Physical Layer Specifications—Amendment: Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation”, IEEE Std 802.3ae—2002.
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