Coded data generation or conversion – Digital code to digital code converters – Adaptive coding
Reexamination Certificate
2001-08-03
2003-06-24
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Adaptive coding
C712S300000
Reexamination Certificate
active
06583735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention is related to a method and apparatus for adaptive signal encoding schemes based on the capacitive coupling effects. The coupling effects include coupling capacitances between adjacent signal lines as well as coupling effects between signal lines and a metal layer. The invention does not assume any a priori knowledge that is particular to a specific set of signals traversing the signal lines.
2. Description of the Related Art
The following references provide useful background information on the indicated topics, all of which relate to the invention, and are incorporated herein by reference:
International Technology Roadmap for Semiconductors,
1999 Edition, http://www.semichips.org
ews/events/itrs99/, downloaded and printed on Feb. 13, 2001;
Farid N. Najm,
Transition Density: A New Measure of Activity in Digital Circuits,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 2, pp. 310-323, (February 1993);
Milind B. Kamble and Kanad Ghose,
Analytical Energy Dissipation Models For Low Power Caches,
IEEE Proceedings of Symposium on Low Power Electronics and Design, pp. 143-148 (1997);
Kiyoo Itoh, Katsuro Sasaki and Yoshinobu Nakagome,
Trends in Low
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Power RAM Circuit Technologies,
Proceedings of the IEEE, Vol. 83, No. 4, pp. 524-543 (April 1995);
Tony Givargis, Frank Vahid and Jörg Henkel,
Fast Cache and Bus Power Estimation for Parameterized System
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On
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A
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Chip Design,
Proceedings of IEEE/ACM Conference on Design Automation and Test in Europe (DATE00) (March 2000);
Ricardo Gonzales and Mark Horowitz,
Energy Dissipation in General Purpose Processors,
IEEE Proceedings of Symposium on Low Power Electronics, pp. 12-13 (1995);
V. Tiwari,
Logic and System Design for Low Power Consumption,
Ph.D. thesis, Princeton University, November 1996;
Mircea R. Stan and Wayne P. Burleson,
Bus
-
Invert Coding for Low
-
Power I/O,
IEEE Transactions on VLSI Systems, Vol. 3, No. 1, pp. 49-58 (March 1995);
Preeti R. Panda and Nikil D. Dutt,
Low
-
Power Memory Mapping Through Reducing Address Bus Activity,
EEE Transactions on VLSI Systems, Vol. 7, No. 3, pp. 309-320 (September 1999);
Paul P. Sotiriadis and Anantha Chandrakasan,
Low Power Bus Coding Techniques Considering Inter
-
wire Capacitances,
Proceedings of EEE Conference on Custom Integrated Circuits, pp. 507-510 (2000);
Ki-Wook Kim, Kwang-Hyun Baek, Naresh Shanbhag, C. L. Liu and Sung-Mo Kang,
Coupling
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Driven Signal Encoding Scheme for Low
-
Power Interface Design,
Proceedings of IEEE 37
th
Design Automation Conference, pp. 318-321 (2000);
L. Benini, A. Macii, E. Macii, M. Poncino and R. Scarsi,
Synthesis of Low
-
Overhead Interfaces for Power
-
Efficient Communication over Wide Buses,
Proceedings of IEEE 36
th
Design Automation Conference, pp. 128-133 (1999);
Huzefa Mehta, Robert M. Owens and Mary J. Irwin,
Some Issues In Gray Code Addressing,
Proceedings of IEEE Conference, 6
th
Great Lakes Symposium on VLSI, pp. 178-181 (1996);
Ching-Long Su, Chi-Ying Tsui, and Alvin Despain,
Saving Power in the Control Path of Embedded Processors,
IEEE Design & Test Magazine, Vol. 11, No. 4, pp. 24-31 (Winter 1994);
Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto and Cristina Silvano,
Asymptotic Zero
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Transition Activity Encoding for Address Busses in Low
-
Power Microprocessor
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Based Systems,
Proceedings of IEEE Conference, 7
th
Great Lakes Symposium on VLSI, pp. 77-82 (1997);
Enric Musoll, Tomás Lang and Jordi Cortadella,
Working
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Zone Encoding for Reducing the Energy in Microprocessor Address Buses,
IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 568-572 (December 1998);
William Fornaciari, Donatella Sciuto and Cristina Silvano,
Power Estimation for Architectural Exploration of HW/SW Communication on System
-
Level Buses,
Proceedings of IEEE International Workshop on HW/SW Co-Design, pp. 152-156 (1999);
Andrea Acquaviva and Riccardo Scarsi,
A Spatially
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Adaptive Bus
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Interface for Low
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Switching Communication,
Proceedings of IEEE International Symposium on Low Power Electronics and Design, pp. 238-240 (2000);
Sumant Ramprasad, Naresh Shanbhag and Ibrahim N. Hajj,
A Coding Framework for Low
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Power Address and Data Buses,
IEEE Transactions on VLSI Systems, Vol. 7, No. 2, pp. 212-221 (June 1999);
Yan Zhang, Wu Ye and Mary J. Irwin,
An Alternative Architecture For On
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Chip Global Interconnect: Segmented Bus Power Modeling,
Conference Record (Signals, Systems & Computers) of 32
nd
Asilomar Conference, pp. 1062-1065 (1998); and
Mircea R. Stan and Wayne P. Burleson,
Low
-
Power Encodings for Global Communication in CMOS VLSI,
IEEE Transactions on VLSI Systems, Vol. 5, No. 4, pp. 444-455 (December 1997).
There will now be provided a discussion of various topics to provide a proper foundation for understanding the invention.
Minimizing power consumption of digital systems has become a crucial task. From a technology point of view, high power and/or energy consumption can cause integrated circuits to overheat, resulting in an acceleration of electro-migration processes and other undesirable effects. An integrated circuit with a high consumption of energy will likely malfunction.
From an application point of view, the power/energy consumption of a system is crucial. For example, consider mobile computing devices: if the power/energy consumption is low, operational time between recharges is extended. This extended operational time allows the implementation of additional functionality that previously could not be added due to energy constraints (e.g., a battery's limited amount of energy).
Many consumer devices are designed as a Systems-On-a-Chip (SOC) that comprise multiple system components (e.g., CPU, MPEG decoder, etc.) on a single silicon substrate. As SOC functionality and complexity increases, so does the communication infrastructure necessary for efficient (i.e., fast) information exchange information between those components. As a result, the amount of energy that the SOC communications infrastructure (e.g., signal groups, bus lines, etc.) consumes has a significant impact.
The trend towards deep sub-micron designs of 0.18 microns or less also contributes to the increasing impact of power/energy consumption of the communication infrastructure. Effects that could be neglected in the past are now becoming increasingly important. One effect is the coupling capacitance that exists between physically close signal lines. The spatial closeness of signal lines increases the wire-to-wire capacitance such that it may exceed the base capacitance of a wire, i.e., the wire-to-metal-layer capacitance. In this context, a “metal layer” is a layer on integrated circuit layout having a zero voltage potential.
For CMOS circuits, it is implicitly assumed that power consumption is due to switching activity only. Leakage currents, however, might become a larger source of power consumption in the future. At present, switching activity in CMOS is the primary source of power consumption.
With these coupling effects in mind, the number of switching activities of a group of signals (e.g., a series of transitions on a group of address bus lines) does not necessarily reflect the power that is consumed by the group of signals. As noted by Najm, this is true for non-deep sub-micron designs. In this context, a non-deep sub-micron design is a design wherein the spatial proximity of signal lines or devices does not lead to coupling capacitances that are in the same order of magnitude as the intrinsic (i.e., base) capacitances. Hence, encoding mechanisms for reducing signal line power consumption that rely solely on minimizing the number of transitions are not efficient any more. In fact, any efficient encoding scheme for deep sub-micron signal lines should be based on a precise physical signal line model.
Power modeling/optimization of SOCs has been addressed at various levels of abstraction, as well as for various system components. Kamble et al. discuss analytical models for estimating th
Henkel Jörg
Lekatsas Haris
NEC Corporation
Nguyen John B
Tokar Michael
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