Patent
1995-08-10
1997-04-22
Heckler, Thomas M.
395280, G06F 1338
Patent
active
056236450
ABSTRACT:
An apparatus and method for acquiring data information provided by a synchronous bus transaction with at most zero hold-time. A transparent latch circuit is used to capture bus transaction information before a rising clock edge of the next clock cycle following a bus transaction request and a data phase starting signal thereby meeting the zero-hold requirement. At the same time, bus transaction information is decoded to determine whether the current phase is a data phase, data information is present in the current bus transaction, memory addresses presented are within an allowable range, and bus transaction command is of the type recognized. If all the above conditions are met, the information captured by the transparent latch circuit is registered by a synchronous flip-flop circuit as valid data information.
REFERENCES:
patent: 5361267 (1994-11-01), Godiwala et al.
patent: 5457694 (1995-10-01), Smith
Kanekal Hemanth G.
Yip Thomas C.
Cirrus Logic Inc.
Heckler Thomas M.
Nguyen Frank D.
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