Method and apparatus for achieving 50% duty cycle on the...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control

Reexamination Certificate

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Details

C327S172000, C327S054000, C327S055000, C330S257000, C330S260000

Reexamination Certificate

active

07965118

ABSTRACT:
Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier. According to another embodiment, a CML-to-CMOS converter circuit is described, including a limiting differential amplifier for generating a single ended clock signal from a differential common mode clock signal, wherein the single ended clock signal has a duty cycle, a low-pass filter for generating a measurement of the duty cycle of the single ended clock signal, and a second differential amplifier for (i) comparing the measurement with a reference voltage and (ii) generating a differential bias current signal in response to the comparison.

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