Data processing: structural design – modeling – simulation – and em – Emulation
Reexamination Certificate
1998-06-12
2001-01-09
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Emulation
C703S020000, C703S022000, C703S027000
Reexamination Certificate
active
06173247
ABSTRACT:
BACKGROUND
With the explosive growth of the Digital Signal Processor (DSP) market, there has been a direct increase in the use of fixed-point digital signal processors in a variety of industries, such as telecommunications, speech/audio processing, instrumentation, military, graphics, image processing, control, automotive, robotics, consumer electronics and medical technology. In general, fixed-point DSP's compared to floating-point DSP's are less expensive, use less power and less space. One advantage of a floating-point DSP is a smaller development cost (i.e., man hours), however, this is with the compromise of a greater production cost. Thus, if possible, companies are using and will use fixed-point DSP's for their products. In the near future, engineers (users) will be faced with the challenge of real-time implementations of complex DSP algorithms (i.e., functions or operations) on fixed-point DSP'S.
SUMMARY OF THE INVENTION
The present invention is the outcome of Applicants' desire to decrease the development time of fixed-point implementations.
The invention method enables the following development cycle model for the real-time implementation of a given operation/function on a fixed-point DSP:
1) floating-point model
2) fixed-point model
3) real-time implementation.
The development time is drastically reduced using the invention method with the above development model or one similar thereto. By decreasing development time, Applicants have narrowed the advantage gap between floating-point DSP's and fixed-point DSP's.
Besides being able to model a fixed-point DSP in a C++ environment, a supporting library (or more generally, working vector space) expedites the conversion of an operation (or function) from a floating-point model to a given fixed-point processor model; from step
1
to step
2
in the above development model. In a preferred floating-point model, the invention defines a C++ class, say, for example, “FLOAT”. The invention attaches various data members to the defined class (e.g., FLOAT) to keep track of pertinent information for transforming a floating-point model to a fixed-point model. Moreover, suppose the floating-point model of an operation/function calls N modules, then one needs a fixed-point model for each of the N modules under each fixed-point processor to be modeled.
The present invention supports situations when one wants to convert only certain modules to a fixed-point processor model while leaving other modules as a floating-point model, such as a fixed-point encoder and a floating-point decoder. In order to accomplish the dual existence of a fixed- and floating-point model, the invention method creates a C++ interface class, to do exactly that, interface a fixed-point module with a floating-point module. In terms of linear algebra, the interface class acts as a transformation operator, transforming from the invention fixed-point model space to a floating-point model space of the present invention.
Thus, the present invention provides a computer method and apparatus for modeling a digital signal processor. In particular, the present invention employs a high level computing language for representing operation of the target processor. Further, the invention provides representations that are bit-wise matchable to machine language output of the target digital processor. The invention representations being bit-wise matchable and in the high level language enables users to directly read and match model executed steps to actual operation steps of the target digital processor.
In the preferred embodiment, the present invention computer system and method models a digital processor by:
(a) providing data representations and operations of a target processor (such as in a library or other source); and
(b) using a high level programming language, modeling the data representations and operations of the target processor in a manner such that model generated data is bit-wise matchable to data generated by the target processor, and in human readable terms instead of machine code.
In accordance with one aspect of the present invention, the step of modeling is incremental such that a first set of certain data representations and operations of the target processor is modeled using the high level programming language to form an intermediate model of the target processor. Subsequent to the formation of the intermediate model, at least a second set of data representations and operations of the target processor is modeled using the high level programming language to increment the intermediate model toward a final desired model of the target processor, and so forth with each further subsequent set of data representations and operations.
In accordance with another aspect of the present invention, the target processor data representations and operations are preferably provided in a hierarchy or power class. As such, the library or source of the target processor data representations and operations is formed by the steps of:
for a given source processor, (a) determining each distinct fixed bit length data representation, and (b) grouping the determined distinct data representation to form a set;
for each target processor, repeating steps (a) and (b) such that respective sets are formed; and
forming a hierarchy of the formed sets by correlating one set to another, such that a base class with depending subclasses are generated and form the hierarchy, each set being defined by one of the base class and a subclass.
REFERENCES:
patent: 4135242 (1979-01-01), Ward et al.
patent: 4893267 (1990-01-01), Alsup et al.
patent: 5295222 (1994-03-01), Wadhwa et al.
patent: 5560013 (1996-09-01), Scalzi et al.
patent: 5583983 (1996-12-01), Schmitter
patent: 5613098 (1997-03-01), Landau et al.
patent: 5732005 (1998-03-01), Kahle et al.
patent: 5768593 (1998-06-01), Walters et al.
patent: 6011872 (2000-01-01), Qian et al.
patent: 0 718 757 (1996-06-01), None
Ombres, D., “C and C++ Extensions Simpilfy Fixed-Point DSP Programming,”EDN,pp. 135-138, Oct. 10, 1996.
“Digital Signal Processing Solutions Support,” http://www.ti.com/sc/docs/dsps/develop/3rdparty/consult/458tarta.htm, (downloaded Jun. 3, 1997).
Robe and Irwin, ‘SIMULINK Modules that Emulate Digital Controllers Realized with Fixed-Point or Floating-Point Arithmetic’, May 1994.
Maruudis, A.S., “FACT™: A C++ Environment for Accurately Modeling Fixed-Point Digital Signal Processors,” presented at conference on Intelligent Methods for Signal Processing and Communications, Universidad de Vigo, Baiona (Vigo), Spain, Jun. 24-26, 1996.
Maurudis, A.S., “FACT™: A C++ Environment for Accurately Modeling Fixed-Point Digital Signal Processors,” The Proceedings of the 7th International Conference on Signal Processing Applications & Technology, vol. 1, p. 846-851, Boston, Mass., U.S.A., Oct. 7-10, 1996.
Marurudis, A.S., “An Efficient Vector-Space Approach for Accurately Modeling Fixed-Point Digital Signal Processors,”1996 IEEE TENCON—Digital Signal Processing Applications,pp. 659-664 (Nov. 27-29, 1996).
Fortune and Van Wyk, ‘Efficient Exact Arithmetic for Computational Geometry’, 0-89791-583-6/93/0005/0163, 1993, pp. 163-172.
Lee and Ho, ‘Target bit matching for MPEG-2 Video Rate Control’, IEEE 0-7803-4886-9/98, 1998, pp. 66-69.
Kambi and Follet, ‘Error analysis of filters implemented with floaing point arithmetic’, IEEE 0-8186-5320-5/94. 1994, pp. 47-51.
Mark B. Kraeling, ‘Fixed-point math in time-critical C applications’, ISBN 0-7803-3274-1, pp. 587-593.
Harton and Kapuscinski, ‘BEC++: A software tool for increaded flexibility in algorithm development’, IEEE 0-7803-5651-9/99, pp. 67-69.
Chris Edward, ‘Library to model DSP algorithms’, Electronics Times, n 908, p14, Jun. 1998, 1 page.
Robe and Irwin, ‘SIMULINK, Modules that emulae digital controllers realized with fixed-point or floating-point arithmetic’, IEEE paper; 0-8186-5320-5/94, 1994, pp. 337-341.*
Della Morte James T.
Della Morte, Jr. John O.
Maurudis Anastasios S.
DSP Software Engineering, Inc.
Hamilton Brook Smith & Reynolds P.C.
Knox Lonnie A.
Teska Kevin J.
LandOfFree
Method and apparatus for accurately modeling digital signal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for accurately modeling digital signal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for accurately modeling digital signal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2516610