Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-12-29
2001-10-02
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S368000
Reexamination Certificate
active
06298101
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer data storage devices, and more particularly to accurately initiating the generation of a series of data detection windows in response to the detection of a synchronization pattern in a data stream corresponding to data stored in a disk drive.
BACKGROUND OF THE INVENTION
Users require accurate data storage and retrieval from their peripheral devices. Moreover, they desire being able to accurately store more information on these devices. Various encoding techniques have been developed to increase the data storage density on a peripheral device. The efficiency of these techniques is dependent in part on the accuracy of circuits used for identifying the location and timing of data within the signal. Increasing the accuracy will allow the storage of more information in the peripheral device.
One method of storing data on a disk uses a phase-encoded stream of data, where binary data is encoded into the relative timing between pulses in the signal stream. In this configuration, the data stream comprises overhead and data information. The overhead information is used to identify the location or timing of the data information, with the data information being partitioned into a stream of cells, with each cell representing a bit of data. Each cell is further divided into two detection windows, one of which being assigned a value of “1” and the other being defined a value of “0”. The value of the data bit is determined by the presence or absence of a pulse within these two detection windows of the cell. With a perfect signal (i.e., no noise), one data pulse occurs within each bit cell, either in the early or late detection window.
A decoder digital circuit is generally used to covert the phase-encoded signal into a digital sequence of bits (i.e., 1's and 0's) representing the stored data. A typical decoder performs several functions, including synchronizing the digital pulses in the phase-encoded signal to a precise-frequency digital clock signal; creating a sequence of detection windows; synchronizing the detection windows to the digital data (usually via some kind of synchronization pattern contained in the overhead portion in the digital signal); and converting the phase-encoded data to the binary data bit values based on the pulse locations relative to the detection windows. In addition, the decoder sometimes maintains synchronization between the detection windows and digital data, usually by shifting the time location of the detection windows early or late based on timing of the digital data signal.
A sync pattern is used to define the start of the user data within the data signal. A sync pattern generally consists of a series of pulses timed in a way that would not match any valid data pattern, thus making the sync pattern uniquely identifiable within the data signal. In many applications, the sync pattern is repeated at regular (or possibility non-regular) intervals in which case there are multiple segments of user encoded data. Such as the case in disk drive systems with embedded servo fields where the servo data is stored in the servo fields which are repeated at regular intervals around the disk.
In an ideal system, the first bit of user data occurs at a fixed time interval after the sync pattern, which allows the detection windows to be initially aligned, or synchronized to the data signal via the sync pattern. Such is the case in both pulse and phase encoded data signals.
In working systems, however, the bit cell detection window timing are typically derived from a clock signal via digital counting circuits, whereas the data signal pulses are derived from a separate source not necessarily synchronized with the clock signal. Because of this, the pulses within the data signal are not precisely aligned with the clock signal and thus are also not precisely aligned with the detection windows. When combined with noise which typically exists in a data signal, this synchronization error can cause mis-detection of the phase encoded data inducing error into the system.
This problem occurs in disk drive systems where the data does not always occur at regular, evenly spaced intervals. In a disk drive system, it is often the case the timing between data pulses is skewed such that a slight but consistent time error exist between data pulses. For example this scenario occurs in a data signal being derived from magnetic transitions on a disk that is rotating a speed somewhat differently than the design nominal speed. Although the error between any two adjacent pulses might be small, the error will accumulate throughout the data pattern such that for longer patterns the error becomes significant. This error situation is exaggerated when the initial alignment of the sync detection signal and the generation detection windows are not exactly aligned.
SUMMARY OF THE INVENTION
According to the invention, a new method and apparatus provide a more precise initial alignment between the detection windows and a synchronization pattern contained within a data signal. More specifically, the portion of the decoder circuit which generates the detection windows is clocked at some higher multiple of the nominal clock frequency, typically two or more times, in order to provide higher resolution for aligning the timing of the detection windows relative to the data signal. In this manner, the synchronization delay is minimized, and the detection window location relative to the data signal will be improved (i.e., the data pulses will be more centered within the detection window). Therefore, noise in the data signal will be less likely to cause detection errors. By providing such a robust system, the overall error rate is reduced and system performance improved.
It should be noted that the present invention is equally applicable to both phase and pulse encoded data, and can be used in many different applications. An embodiment of the present invention described herein relates to encoding servo position data located on the disks and in disk drive products used for data storage. However, the present invention is not limited to this embodiment. Rather, the teachings of this invention may be applied wherever phase or pulse encoded data is used in keeping within the scope and spirit of the present invention.
The present invention uses a high frequency clock for a portion of the decoder circuit responsible for lo providing the timing between the detection of the sync pattern and the generation of detection windows. The remaining circuitry of the decoder circuit is clocked at the nominal clock rate. By only clocking a portion of the decoder circuit at the high frequency clock rate as taught by the present invention, a cost effective system design is possible while achieving the desired enhanced performance.
In one embodiment of the present invention, a presettable down counter clocked at the high frequency rate is used to provide the timing between the detection of the sync pattern and the generation of the detection windows. The presettable down counter is set each time a data pulse occurs to a predetermined value corresponding to a programmable delay from the last data pulse in the sync pattern to the start of the first detection window. When the counter reaches zero (as determined by the counter or a comparator element) and only if an enable and start detection windows control signal is true at the same time, then the first detection window is started. Typically, the enable and start detection windows signal will go true before the counter reaches zero, and therefore, the start of the first detection window is based on the counter equaling zero condition. Because the counter is running at the higher clock frequency, and because this counter's start time is based on a data pulse, the start time of the first detection window will be more precisely located relative to the data signal, reducing the error rate and improving the performance of a data detection system.
Because the counter and detection window generation portion of the decoder circuit i
Adaptec, Inc.
Bocure Tesfaldet
Patton & Boggs LLP
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