Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2003-06-25
2004-08-17
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S113000
Reexamination Certificate
active
06778119
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention relates generally to mix signal processing and more particularly to digital-to-analog conversion.
2. Description of Related Art
Digital-to-analog converters are known to be used in a wide variety of mix signal (i.e., analog and digital signaling) applications. For example, digital-to-analog converters are used in all digital audio equipment to convert digital audio data into analog audio signals, which can be rendered audible via a speaker. Further, digital-to-analog converters are used in video equipment to convert digitized video signals into analog video signals that may be subsequently rendered visible on a CRT (cathode ray tube) display.
As is also known, current mode digital-to-analog converters are quite popular due to their ease of implementation using CMOS integrated circuit technology. A current mode digital-to-analog converter includes a plurality of equal valued current sources, gating circuitry, and a differential amplifier. The gating circuitry includes a plurality of cascaded flip-flops and transistors, where the flip-flops serially receive a digital input and, on a cycle-by-cycle basis, produce a collective output that gates the transistors, which, in turn, enables the current sources to drive either the inverting or non-inverting input of the differential amplifier. The differential amplifier includes a feedback network to establish an analog output voltage based on the cycle-by-cycle current sourcing of the inverting and non-inverting inputs. As such, the analog output is computed based on a 1's density of the digital input (i.e., the number of logic is currently contained in the gating circuitry). Accordingly, the more 1s in the current digital input, the greater the analog output and, conversely, the less 1s in the current digital input, the lower the analog output.
For example, a current mode digital-to-analog converter that includes four equally valued current sources can convert a current 4-bit digital input value into one of five analog output states. The lowest of the five analog output states is achieved when the four current bits of the digital input are all 0s (e.g., 0000). The next lowest analog output state is achieved when one of the four current bits is 1 and the remaining bits are 0s (e.g., 1000, 0100, 0010, or 0001). The middle level analog output is achieved when two of the four current bits are 1s and the other two bits are 0s (e.g., 1100, 1010, 1001, 0011, 0101, 0110). The second highest state of the analog output is achieved when three of the four bits are 1s and the remaining bit is a 0 (e.g., 0111, 1110, 1011, 1101). The highest of the five analog output states is achieved when the four current bits of the digital input are all 1s (e.g., 1111). Accordingly, the greater number of current sources, the more granular the analog output.
While current mode DACs are popular due their ease of implementation using CMOS technology, they have certain limitations and/or drawbacks. For example, the flip-flops and transistors of the gating circuitry do not produce inversely identical signals. Accordingly, the current provided to the inverting and non-inverting inputs of the differential amplifier are not inversely identical signals. This imbalance, if not corrected, causes a distortion of the digital to analog conversion process and illustrated in
FIGS. 1 and 2
.
FIG. 1
is a schematic block diagram of a cell of the gating circuit of a prior art current mode digital-to-analog converter. The cell includes 2N-channel transistors and a D flip-flop, where the transistors are coupled to one of the current sources. The D flip-flop is clocked based on the rate of the incoming digital input and receives one bit of the digital input (b
n
) from a preceding cell in the gating circuitry or, if the cell is the first cell in the gating circuitry, receives the one bit of the digital input from a digital source. Thus, at the clocking of the D flip-flop, if the input bit is a logic 1, the Q output is high and the Q bar output is low producing a current (I), which would be provided to the inverting input of the differential amplifier. If, however, the input is a logic 0, and Q output is low and the Q bar output is high producing at I bar current, which is provided to the non-inverting input of the differential amplifier. While the N-channel transistors are generally matched, the drive circuitry of the D flip-flop and the imperfections of the transistors yields different rise and fall times for generation of I and I bar.
FIG. 2
illustrates a timing diagram for the cell of the prior art digital-to-analog converter of FIG.
1
. The diagram includes a clock signal, the bit input, the Q output, the Q bar output, the current I output and the current I bar output. The D flip-flop is rising edge triggered such that at every rising edge of the clock signal, the value of the input bit of the D flip-flop is latched into the Q output of the flip-flop. As shown, at the first rising edge of the clock, the digital input is a logic 1 thus, causing the Q output to rise to a logic 1 and the Q bar output to fall to a logic 0. As shown, however, the rise time is faster than the fall time. Conversely, the fall time may occur faster than the rise time. In this illustration, with the rise time being faster than the fall time, the resulting currents are imbalanced since the non-inverting current (I) rises faster than the inverted current (I bar) falls.
To overcome this imbalance of rise and fall times, current mode DACs utilize return-to-zero (RTZ) circuitry. As is known, RTZ circuitry forces the outputs of each cell of the gating to be set to zero before a next bit is processed. By staring each new cycle at zero, the adverse effects of the imbalanced rise and fall times are substantially overcome.
While RTZ circuitry substantially overcomes the adverse effects of imbalanced rise and fall times, it requires time to set the outputs to the zero state. As the bit rates increase for DACs, the RTZ processing time is consuming a greater percentage of the clock cycle, thereby reducing the time for the digital to analog conversion. At and above certain data rates, the RTZ processing time is too great, thus rendering this solution to the imbalanced rise and fall time problem unusable. Further, RTZ circuitry consumes power to perform it function, which, for battery-operated devices, reduces battery life.
Therefore, a need exists for a method and apparatus that reduces the current imbalances within digital-to-analog converters without an RTZ circuit and/or reduces power consumption.
BRIEF SUMMARY OF THE INVENTION
The accurate digital-to-analog conversion of the present invention substantially meets these needs and others. In one embodiment, a digital-to-analog converter includes a differential amplifier, a plurality of current sources, and a conversion control circuitry. The differential amplifier includes a non-inverting input, an inverting input, a non-inverting output, an inverting output, and a gain network coupled to the inputs and outputs. The conversion control circuitry operably couples a 1st set of the plurality of current sources to the inverting input or to the non-inverting input of the differential amplifier in accordance with a 1st set of bits of a digital input and couples, via at least one inversion, a 2
nd
set of the plurality of current sources to the inverting or non-inverting input of the differential amplifier based on a 2
nd
set of bits of the digital input. For example, the conversion control circuitry couples half of the current sources to the differential amplifier in one manner and the other half of the current sources to the differential amplifier in a second manner to substantially eliminate the adverse effects caused by imbalances in rise and falls times without the use of an RTZ circuit, which has the further benefit of reduced power consumption and smaller die area.
REFERENCES:
patent: 3857021 (1974-12-01), Wilensky et al.
patent: 5028926 (1991-07-01), Tokuhiro
patent: 5148161 (1992
Jeanglaude Jean Bruner
Markison Timothy W.
Sigmatel, Inc.
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