Method and apparatus for accessing internal integrated circuit s

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G06F 1100

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057176990

ABSTRACT:
A method and apparatus for analyzing a programmable logic device (PLD) that provides access to internal nodes of the circuit. The method and apparatus in accordance with the present invention uses a shadow programmable logic device to emulate the target PLD while coupling input and output terminals of the shadow PLD so as to provide more information about the target PLD than can be obtained from the target PLD itself. Also, the shadow PLD can implement internal stimulus and/or response functions to provide improve analyzing capability not possible with the target PLD alone.

REFERENCES:
patent: 4853626 (1989-08-01), Resler
patent: 5621312 (1997-04-01), Achor et al.

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