Method and apparatus for accelerating arbitration in a serial bu

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

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370447, 370462, 370471, H04J 326

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active

058020489

ABSTRACT:
Methods and circuitry for arbitrating for control of a serial bus are described. According to one embodiment, one or more nodes of a serial bus are provided with a mechanism for discriminating between data packets and acknowledge packets. If a packet transmitted, repeated, or received by the node is a data packet, the node remains idle for a subaction gap time T.sub.sa to better ensure that the expected acknowledge packet is allowed to successfully propagate throughout the serial bus to the source node. If the packet transmitted by the node is an acknowledge packet, the node is free to begin the arbitration phase of the next subaction if there are no other conditions that prevent further arbitration by that node. To discriminate between data packets and acknowledge packets, a counter is used to determine the length of a transmitted packet, and the length is compared to the expected length of an acknowledge packet. If the length is equal to the expected length of an acknowledge packet, the packet is an acknowledge packet.

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Patent Abstracts of Japan; 60 194642 (Sharp) Oct. 03, 1985; see abstract.
IEEE Standards Document P1394, "High Performance Serial Bus", Draft 7.1 vol. 1. pp. 105-112.

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