Method and apparatus for a testable high frequency synchronizer

Details Method and apparatus for a testable high frequency synchronizer Method and apparatus for a testable high frequency synchronizer

1997-06-27

1999-11-16

Tse, Young T.

Pulse or digital communications

Synchronizers

326 93, 327142, 327145, 713400, H04L 700

Patent

active

059870818

ABSTRACT:
A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.

REFERENCES:
patent: 4873703 (1989-10-01), Crandall et al.
patent: 5101419 (1992-03-01), Lowe et al.
patent: 5122694 (1992-06-01), Bradford et al.
patent: 5487092 (1996-01-01), Finney et al.
patent: 5504927 (1996-04-01), Okamoto et al.
Kleeman, Lindsay: The Jitter Model for Metastability and its Application to Redundant Synchronizers 1990 pp. 930-942.
Kleeman, Lindsay and Cantoni, Antonio: Metastable Behavior in Digital Systems 1987 pp. 4-19.

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