Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-04-28
2002-09-24
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S295000, C327S256000, C327S239000
Reexamination Certificate
active
06456138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to radiation hardened integrated circuits and, more particularly, to clock generation circuits for radiation hardened integrated circuits.
2. Related Art
Increasingly, space-based communication systems are including integrated circuits (IC) made in advanced deep sub-micron Field Effect Transistor (FET) technology. Typically, these ICs are in the insulated gate silicon technology commonly referred to as complementary metal oxide semiconductor (CMOS). CMOS ICs are advantageous in that they are high speed and low power. The CMOS ICs use little power compared to what other technologies require for comparable speed and function.
In a space-based environment, however, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances. These circuit disturbances are known as single event effects (SEE) and, as single event upsets (SEU) when corrupting data in storage elements. Radiation hardened latches are well known and are used, effectively, to reduce or to eliminate SEU in space-based IC registers, latches and other storage elements. These radiation hardened storage elements are designed to protect from disturbance what is stored in them in spite of any cosmic particle hits that the storage elements might sustain.
However, over time, as circuit performance has increased, the propagation delay through the logic between the radiation hardened latches or registers has been reduced to within an order of magnitude of the duration of an SEE. For example, a pipelined logic chip operating at 200 MHz can have 3-3.5 nanoseconds allocated for logic propagation delays between registers. A single event upset occurring in the logic can cause an invalid result for 0.5-1.0 nanoseconds because this is a significant amount of time with respect to a pulse width. Such an event occurring in a clock distribution chain causes a more widespread and potentially a much more serious result.
Typically, chip clocks are received by a receiver connected to a bonding pad of the IC. The receiver buffers and redrives the clock, typically, to multiple locations on the chip. At each of these locations, the clock is again buffered and redriven. This rebuffered clock can further distributed to multiple locations, where it can again be rebuffered and redriven. The clock distribution can be represented as a tree spreading out from the original receiver.
The effects from an event occurring in a clock tree can cause a transient in the clock signal on part of the clock tree of approximately 0.5 nanoseconds, which can appear as a false clock pulse. Further, the number of latches and registers affected by the false clock pulse is random and depends on where in the tree the event occurs. Such a false clock pulse can clock registers causing the registers to latch invalid data. The invalid latched data can be passed from the initial registers through the next logic stage. This can result in multiple uncorrectable multi-bit logic errors.
The severity of this problem only increases with greater levels of very large scale integration (VLSI) circuit integration because these higher levels of integration achieve higher performance through smaller features. For example, with circuits operating in the 1 GHz clock range, a single event could wipe out an entire clock cycle for the affected part of the IC logic. Thus, it can be seen that clock tree SEE immunity is critical to preventing logic errors.
For example,
FIG. 1
illustrates a typical state of the art scan d-flip-flop (scan dff)
100
. The scan d flip-flop
100
includes a 2:1 multiplexer
102
, which is coupled to a first level sensitive latch
104
. The first level sensitive latch
104
is coupled to a second level sensitive latch
106
. The scan dff
100
is clocked by a clock signal
107
. The clock signal
107
is split into complementary signals by inverting clock signal
107
with inverter
108
. The complementary clock signals are provided to first level sensitive latch
104
and second level sensitive latch
106
, gating first and second pairs of pass gates
110
,
112
and
114
,
116
, respectively.
When selected, an input DATAIN
118
passes through the 2:1 multiplexer
102
to the first pair of pass gates
110
,
112
as complementary outputs
120
,
122
of multiplexer
102
. When the clock signal
107
is low, pass gates
110
,
112
, are turned on so that data and complementary outputs
120
,
122
are passed to first level sensitive latch
104
and, tentatively, are stored therein. With the clock signal
107
low, the second pair of pass gates
114
,
116
are contemporaneously turned off, and isolate the second level sensitive latch
106
from outputs
124
,
126
of the first level sensitive latch
104
.
The rising edge of clock signal
107
turns on the second pair of pass gates
114
,
116
as the output of inverter
108
falls, simultaneously, to turn off the first pair of pass gates
110
,
112
. When the first pair of pass gates
110
,
112
are turned off, the complementary outputs
120
,
122
are isolated from the first level sensitive latch
104
and, so, data is latched in the first level sensitive
101
latch
104
. When the second pair of pass gates
114
,
116
are turned on, outputs
124
,
126
of the first level sensitive latch
104
are passed to the second level sensitive latch
106
. The state of outputs
124
,
126
, is stored, tentatively, in the second level sensitive latch
106
and, simultaneously, is passed out on an output DATAOUT
128
. When clock signal
107
falls, on the next clock cycle, the second pair of pass gates
114
,
116
are turned off, isolating the second level sensitive latch
106
from the outputs
104
,
126
of first level sensitive latch
104
, latching data in the second level sensitive latch
106
to complete the clock cycle.
Normally, when the clock signal
107
is well behaved with regularly spaced high and low periods, it is sufficient that data provided to the input DATAIN
118
meet setup (i.e., be valid for a specified period prior to the rise of clock signal
107
) and hold (i.e., remain valid for a specified period after the rise of clock signal
107
) timing requirements. At any time, other than this window around clock signal
107
rising, the state of input DATAIN
118
is specified as a “don't care” condition.
Unfortunately, an upsetting event occurring in the clock tree prior to clock signal
107
can cause a false clock pulse on clock signal
107
. Since input DATAIN
118
is specified as a “don't care,” a falling edge of a false clock pulse on clock signal
107
could cause the first level sensitive latch
104
to switch states, inadvertently storing data. Further, when the input clock returns high, that invalid level can be passed to the second level sensitive latch
106
and out of the scan dff
100
on output DATAOUT
128
. The false clock pulse is a pulse perturbated by an SEE.
Thus, for reasons stated above, and for other reasons stated below, which will become apparent to those skilled in the relevant art upon reading and understanding the present specification, what is needed are clock generation circuits with reduced SEE sensitivity.
SUMMARY OF THE INVENTION
The above mentioned problems with clock generation circuits and radiation hardened storage elements and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
In one embodiment of the present invention, a clock splitter circuit includes an event offset delay circuit, a first event blocking filter having inputs coupled to a delayed output and an undelayed output of the event offset delay circuit, and a second event blocking filter having inputs coupled to an inverted delayed output signal and an inverted undelayed output signal of the event offset delay circuit wherein the first event blocking filter has an output coupled to an input of the second event blocking filter and the second event blocking filter has an output coupled to an input
Kazemzader Abbas
Yoder Joseph W.
BAE Systems Information and Electronic Systems Integration Inc.
Cunningham Terry D.
Swidler Berlin Shereff & Friedman, LLP
Tra Quan
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