Method and apparatus for a semiconductor wafer inspection...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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C700S103000, C700S105000, C700S108000, C700S109000, C700S117000, C700S121000, C702S183000, C702S185000, C702S118000, C438S014000, C438S015000, C438S017000, C257S048000, C257S620000

Reexamination Certificate

active

06240329

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to knowledge-based systems, and more particularly to expert systems for use in wafer inspection systems.
BACKGROUND ART
Expert systems are ubiquitous in the manufacturing environment. This is especially true in the semiconductor industry where wafer processing systems require constant monitoring to ensure adequate quality control to maintain acceptable product yields.
Building a knowledge base traditionally requires the services of a knowledge engineer working closely with line operators and support personnel to identify and classify problem-solving approaches. However, there sometimes is resistance to the idea of surrendering the decision-making process which takes place during the monitoring and adjusting of a process. Oftentimes, the expert (i.e. process engineer, line operator, etc.) is uncertain as to the knowledge engineer's formulation of the knowledge base and whether the expert's knowledge is being accurately transferred into the knowledge base. Once the information has been programmed by the knowledge engineer the expert has no control over the resulting knowledge base and adjustments require additional interaction with the knowledge engineer.
Various improvements have occurred during the evolution of knowledge-based systems. In U.S. Pat. No. 4,924,408, for example, a method is described for increasing the execution speed of a knowledge system by compiling the inference engine and the knowledge base into machine-level code. U.S. Pat. No. 4,935,876 a technique for managing knowledge databases as they increase in size due to the accumulation of knowledge. U.S. Pat. No. 5,548,714 discloses a graphically driven user interface wherein users who have no background in expert systems can construct an expert system.
What is needed is a technique for utilizing a knowledge-based system which increases accessibility to the knowledge base by the expert. It is further desirable that the knowledge base can be defined by the expert, absent the assistance of a knowledge engineer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for automated acceptance testing of semiconductor wafers includes specifying a set of rules which define various device failure modes. Each rule includes one or more electrical test parameters and various criteria which define the failure mode. The method further includes selecting a rule and parsing the selected rule to extract the criteria contained in the rule. Next, one or more boolean expressions are created on the fly from the extracted criteria. The boolean expressions are executed to produce boolean results. A pass/fail determination is then made based on the boolean results. In a preferred embodiment of the invention, the method further includes combining some of the electrical measurements to produce a value which is then evaluated via fuzzy logic processing.
A wafer testing system according to the present invention comprises a wafer testing apparatus for making various electrical measurements on semiconductor wafers. A first data store is coupled to the testing device to receive and store the electrical measurements. A second data store contains rules which define various device failure modes. A computing unit includes software for accessing the second data store to create logic statements from attributes contained in the rules and from electrical measurements taken from the first data store. Additional software interprets the logic statements to produce logic results. Further software produces a pass/fail result based on the logic results.


REFERENCES:
patent: 4924408 (1990-05-01), Highland
patent: 4935876 (1990-06-01), Hanatsuka
patent: 5294812 (1994-03-01), Hashimoto et al.
patent: 5483175 (1996-01-01), Ahmad et al.
patent: 5504369 (1996-04-01), Dasse et al.
patent: 5548714 (1996-08-01), Becker
patent: 5568408 (1996-10-01), Maeda
patent: 5831865 (1998-11-01), Berezin et al.
patent: 5844803 (1998-12-01), Beffa
patent: 5923553 (1999-07-01), Yi
patent: 5946213 (1999-08-01), Steffan et al.
patent: 6028994 (2000-02-01), Peng et al.

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