Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2005-05-17
2005-05-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S012000, C257S194000, C257S197000, C438S312000, C438S314000, C438S317000, C438S318000, C438S337000, C438S343000
Reexamination Certificate
active
06894362
ABSTRACT:
Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4and/or SiO2, for reliable HBT emitter p-n junction passivation. Thus, the disclosed HBT process enables scaling of narrow emitter stripe widths down to sub-micron dimensions producing transistors with cut-off frequencies in the range of several hundred GigaHertz.
REFERENCES:
patent: 5412233 (1995-05-01), Dubon-Chevallier et al.
patent: 5648666 (1997-07-01), Tran et al.
patent: 5668388 (1997-09-01), Delage et al.
patent: 6025615 (2000-02-01), Liu et al.
Flynn Nathan J.
Forde Remmon R.
Ward & Olivo
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