Method and apparatus for a reduced iteration decoder

Details Method and apparatus for a reduced iteration decoder Method and apparatus for a reduced iteration decoder

1993-12-20

1996-01-09

Young, Brian K.

Coded data generation or conversion

Digital code to digital code converters

With error detection or correction

H03M 1300

Patent

active

054832365

ABSTRACT:
The present invention is a reduced iteration decoder circuit and method to compute error-locator sequence values for use in the correction of bit errors in Reed-Solomon or BCH coded information. By utilizing special properties of Reed-Solomon code and BCH codes, the decoder circuit of the present invention can detect n symbol errors using approximately n mathematical iterations with substantially reduced decoding processing time. A further reduction of decoding time is achieved by the performance of a substantial portion of the decoding processing in a parallel manner. The present invention may be utilized in digital communication systems and data storage systems or other information systems where Reed-Solomon or BCH encoding is utilized.

REFERENCES:
patent: 4498175 (1985-02-01), Nagumo et al.
patent: 4845713 (1989-07-01), Zook

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