Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-10-15
2001-07-10
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S142000, C327S198000
Reexamination Certificate
active
06259286
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a power-on-reset system, and more specifically, to a power-on reset system that may be powered off during a shutdown.
BACKGROUND
Power-on reset circuits are used to ensure that a circuit is connected to power only when the power is currently good and has been good for some time. Generally power-on-reset circuits must completely and quickly activate to reset the system upon any indication of poor power quality.
Generally, power-on-reset (POR) pulse generation circuits rely on one of three principles. The first principle is tracking of a process threshold voltage, such as a MOSFET Vt. When the voltage is above the threshold, the POR pulse is sent.
A second principle is sensing an absolute voltage level in comparison to a reference voltage. When the absolute voltage is above the reference voltage, the POR pulse is sent.
The third principle is delay. Once an acceptable voltage level is reached through one of the other methods, a staged R-C or clock/counter delay is generated to ensure that voltages have stabilized.
FIG. 1
illustrates one prior art power-on-reset circuit using these principles. This circuit
110
works, assuming that the V
cc
140
voltage rises quickly and monotonically to its maximum value and stays there. Under those conditions, you can choose an RC time constant large enough to guarantee that the Schmitt-trigger gate
120
holds ~RESET
130
low (active) for any specified time after V
cc
140
stabilizes. After the RC time-out, ~RESET goes high (inactive), commencing normal operations.
Conventional power-on reset circuits generally are left running when the circuits are powered down, to detect an external reset of power-up. This results in a less-than-perfect shutdown.
Therefore, an improved power-on reset system may be useful.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a low power power-on reset system.
A method and apparatus for a power-on reset system is described. The power-on reset system comprises a voltage sense circuit for determining whether a voltage level is above a threshold and a write/rewrite verifier circuit for determining whether the voltage level is high enough to write to and rewrite a memory cell content. A power-on reset pulse emitted by the power-on reset system if the voltage level is above the threshold and high enough to write to and rewrite the memory cell. For one embodiment, this is system generates an initial POR pulse upon power-up but can thereafter be selectively disabled and consume zero power.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
REFERENCES:
patent: 5612642 (1997-03-01), McClintock
patent: 5894423 (1999-04-01), Ling et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Le Dinh T.
Triscend Corporation
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