Method and apparatus for a phase/frequency locked loop

Details Method and apparatus for a phase/frequency locked loop Method and apparatus for a phase/frequency locked loop

2006-03-24

2010-11-09

Payne, David C (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C327S147000, C327S156000, C342S103000, C375S215000, C375S294000, C375S327000, C375S376000, C388S911000, C455S260000

Reexamination Certificate

active

07830986

ABSTRACT:
A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.

REFERENCES:
patent: 4291274 (1981-09-01), Suzuki et al.
patent: 4320356 (1982-03-01), Perdue
patent: 5373255 (1994-12-01), Bray et al.
patent: 6219376 (2001-04-01), Zhodzishsky et al.
patent: 2002/0061087 (2002-05-01), Williams
Justin L. Gaither; “A New Programmable Low Noise All Digital Phase-Locked Loop Architecture”; A thesis submitted to Iowa State University; Copyright Justin L. Gaither, 2005; pp. 1-74.

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