Method and apparatus for a monitor that detects and reports...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C703S015000, C716S030000

Reexamination Certificate

active

06889180

ABSTRACT:
The present invention is a monitor that detects a design verification event and reports a status event to a database. One embodiment of the present invention comprises a monitor declaration, zero or more signal declarations, zero or more bus declarations and one or more logic expressions. A logic expression, formulated using the declared signals and buses, is used to evaluate whether a specific verification event has occurred. The present invention further comprises a monitor where the signal of the signal declaration of the monitor is an N-Nary signal. Additionally, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

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U. S. Patent Application entitled “Software Modeling of Logic Signals Capable of Holding More than Values;” Inventors: Blomgren, et al.; U.S. Appl. No. 09/405,618; filed Sep. 24, 1999.
U.S. Patent Application entitled “Multiple State Simulation for Non-Binary Logic;” Inventors: Blomgren, et al.; U.S. Appl. No. 09/405,474; filed Sep. 24, 1999.
U.S. Patent Application entitled “Method and Apparatus that Reports Multiple Status Events With a Single Monitor;” Inventors: Blomgren, et al.; U.S. Appl. No. 09/406,016; filed Sep. 24, 1999.

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